JPS5588170A - Actuation system of process controller output unit - Google Patents

Actuation system of process controller output unit

Info

Publication number
JPS5588170A
JPS5588170A JP16003078A JP16003078A JPS5588170A JP S5588170 A JPS5588170 A JP S5588170A JP 16003078 A JP16003078 A JP 16003078A JP 16003078 A JP16003078 A JP 16003078A JP S5588170 A JPS5588170 A JP S5588170A
Authority
JP
Japan
Prior art keywords
output
time
register
arithmetic unit
actuation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16003078A
Other languages
Japanese (ja)
Other versions
JPS5826046B2 (en
Inventor
Kazuki Okimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP53160030A priority Critical patent/JPS5826046B2/en
Publication of JPS5588170A publication Critical patent/JPS5588170A/en
Publication of JPS5826046B2 publication Critical patent/JPS5826046B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the generation of an error output at the time when the power supply is put to work, by putting off the actuation of an output actuation part by the time when an arithmetic unit performs at least single write operation in an output register at the time of power feed.
CONSTITUTION: To output actuation part 5 in output unit 2 which extracts the control output of a process controller, reset signal 7 is applied from arithmetic unit 1 via delay circuit 8. After reset signal 7 is released, this delay circuit 8 delays the actuation of output unit 2 by the time when arithmetic unit 1 performs at least single write operation in output register 3. Within this delay time, arithmetic unit writes a normal output in register 3 and after the above-mentioned delay time, a normal arithmetic result is read out from register 3 under the control of output actuation part 5. Consequently, the generation of an error signal when the power supply is put to work can be prevented.
COPYRIGHT: (C)1980,JPO&Japio
JP53160030A 1978-12-27 1978-12-27 Start-up method of process control equipment output device Expired JPS5826046B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53160030A JPS5826046B2 (en) 1978-12-27 1978-12-27 Start-up method of process control equipment output device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53160030A JPS5826046B2 (en) 1978-12-27 1978-12-27 Start-up method of process control equipment output device

Publications (2)

Publication Number Publication Date
JPS5588170A true JPS5588170A (en) 1980-07-03
JPS5826046B2 JPS5826046B2 (en) 1983-05-31

Family

ID=15706431

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53160030A Expired JPS5826046B2 (en) 1978-12-27 1978-12-27 Start-up method of process control equipment output device

Country Status (1)

Country Link
JP (1) JPS5826046B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62179735U (en) * 1986-05-02 1987-11-14
JPS63195326U (en) * 1987-05-29 1988-12-15

Also Published As

Publication number Publication date
JPS5826046B2 (en) 1983-05-31

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