JPS5582324A - Automatic power source breaking system dependent upon attachment - Google Patents

Automatic power source breaking system dependent upon attachment

Info

Publication number
JPS5582324A
JPS5582324A JP15617678A JP15617678A JPS5582324A JP S5582324 A JPS5582324 A JP S5582324A JP 15617678 A JP15617678 A JP 15617678A JP 15617678 A JP15617678 A JP 15617678A JP S5582324 A JPS5582324 A JP S5582324A
Authority
JP
Japan
Prior art keywords
cpu
power source
attachment
prescribed time
interrupt request
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15617678A
Other languages
Japanese (ja)
Other versions
JPS5715413B2 (en
Inventor
Tomonari Adachi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP15617678A priority Critical patent/JPS5582324A/en
Publication of JPS5582324A publication Critical patent/JPS5582324A/en
Publication of JPS5715413B2 publication Critical patent/JPS5715413B2/ja
Granted legal-status Critical Current

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  • Power Sources (AREA)

Abstract

PURPOSE: To obtain an automatic power source breaking system which can be used special software, by providing a simple unit which generates an interrupt asynchronously to a CPU periodically by an attachment corresponding to an I/O device.
CONSTITUTION: Attachment ATC corresponding to an I/O is connected to arbitrary chennel unit CH. A CPU executes a processing program; and when timer TM1 reaches a prescribed time, an output signal is issued to issue an asynchronous interrupt request to the CPU through FF1 and interface control circuit ITF. Simultaneously, timer TM2 starts operations to set the waiting state for response from the CPU. When the CPU responds with a form of the instruction for the I/O within a prescribed time, TM2, is reset, and TM1 is operated again. When no response from the CPU is obtained after a prescribed time from interrupt request issuance, FF2 is set to decide that the CPU loses the processing capability for the interrupt request, and power source breaking command PFD or alarm LPA is issued.
COPYRIGHT: (C)1980,JPO&Japio
JP15617678A 1978-12-16 1978-12-16 Automatic power source breaking system dependent upon attachment Granted JPS5582324A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15617678A JPS5582324A (en) 1978-12-16 1978-12-16 Automatic power source breaking system dependent upon attachment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15617678A JPS5582324A (en) 1978-12-16 1978-12-16 Automatic power source breaking system dependent upon attachment

Publications (2)

Publication Number Publication Date
JPS5582324A true JPS5582324A (en) 1980-06-21
JPS5715413B2 JPS5715413B2 (en) 1982-03-30

Family

ID=15622009

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15617678A Granted JPS5582324A (en) 1978-12-16 1978-12-16 Automatic power source breaking system dependent upon attachment

Country Status (1)

Country Link
JP (1) JPS5582324A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6176934U (en) * 1984-10-26 1986-05-23
JPS6226804A (en) * 1985-07-26 1987-02-04 Canon Electronics Inc Transformer installing method

Also Published As

Publication number Publication date
JPS5715413B2 (en) 1982-03-30

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