JPS5587958A - Digital effective value meter - Google Patents

Digital effective value meter

Info

Publication number
JPS5587958A
JPS5587958A JP16334278A JP16334278A JPS5587958A JP S5587958 A JPS5587958 A JP S5587958A JP 16334278 A JP16334278 A JP 16334278A JP 16334278 A JP16334278 A JP 16334278A JP S5587958 A JPS5587958 A JP S5587958A
Authority
JP
Japan
Prior art keywords
pulses
effective value
counter
voltage
frequency converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16334278A
Other languages
Japanese (ja)
Other versions
JPS6253781B2 (en
Inventor
Eisaku Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Komatsu Ltd
Original Assignee
Komatsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Komatsu Ltd filed Critical Komatsu Ltd
Priority to JP16334278A priority Critical patent/JPS5587958A/en
Publication of JPS5587958A publication Critical patent/JPS5587958A/en
Publication of JPS6253781B2 publication Critical patent/JPS6253781B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To perform measurement stable for a long time without caring about drift, by using a voltage-frequency converter, a rate multiplier, etc.
CONSTITUTION: An input signal is squared by a square circuit 10. The squared signal is changed into a number of pulses by a voltage-frequency converter 11. A rate multiplier 12 changes input pulses into those corresponding to a prescribed pulse rate. The latter changed pulses are applied to a counter 13, which sequentially counts the pulses and sends out the counted value to a latch circuit 14 and a memory circuit 15. At every prescribed time, the counted value from the counter 13 is latched by the latch circuit 14 and displayed on an indicator 16 to indicate the effective value of the input signal.
COPYRIGHT: (C)1980,JPO&Japio
JP16334278A 1978-12-26 1978-12-26 Digital effective value meter Granted JPS5587958A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16334278A JPS5587958A (en) 1978-12-26 1978-12-26 Digital effective value meter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16334278A JPS5587958A (en) 1978-12-26 1978-12-26 Digital effective value meter

Publications (2)

Publication Number Publication Date
JPS5587958A true JPS5587958A (en) 1980-07-03
JPS6253781B2 JPS6253781B2 (en) 1987-11-12

Family

ID=15772042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16334278A Granted JPS5587958A (en) 1978-12-26 1978-12-26 Digital effective value meter

Country Status (1)

Country Link
JP (1) JPS5587958A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07248340A (en) * 1994-03-10 1995-09-26 Nec Corp Level detecting circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07248340A (en) * 1994-03-10 1995-09-26 Nec Corp Level detecting circuit

Also Published As

Publication number Publication date
JPS6253781B2 (en) 1987-11-12

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