JPS558608A - Semiconductor memory device - Google Patents
Semiconductor memory deviceInfo
- Publication number
- JPS558608A JPS558608A JP7869178A JP7869178A JPS558608A JP S558608 A JPS558608 A JP S558608A JP 7869178 A JP7869178 A JP 7869178A JP 7869178 A JP7869178 A JP 7869178A JP S558608 A JPS558608 A JP S558608A
- Authority
- JP
- Japan
- Prior art keywords
- control signals
- odd
- circuit
- input
- check
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
- For Increasing The Reliability Of Semiconductor Memories (AREA)
- Detection And Correction Of Errors (AREA)
- Static Random-Access Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
PURPOSE: To make it possible to suppress undershoot by using a check circuit, which is constituted by a gate circuit having the input level clamp function, to check directly input signals of a semiconductor memory element.
CONSTITUTION: Driving circuit 1 which outputs control signals to a semiconductor memory element and check circuit 2 which is constituted by a gate circuit having the input level clamp function and takes control signals as the input are provided, and control signals S1 to Sn and odd/even check signal P are outputted from driving circuit 1 when a request such as data read, data write is issued. Odd/even check circuit 2 checks applied control signals S1 to Sn and odd/even check signal P for odd or even and checks the normalcy of control signals S1 to Sn and simultaneously uses the forward voltage of input clamp diode D to clamp undershoot, which appears in the voltage waveform, to approximately OV when control signals S1 to Sn change from a high level to a low level.
COPYRIGHT: (C)1980,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7869178A JPS558608A (en) | 1978-06-30 | 1978-06-30 | Semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7869178A JPS558608A (en) | 1978-06-30 | 1978-06-30 | Semiconductor memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS558608A true JPS558608A (en) | 1980-01-22 |
Family
ID=13668881
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7869178A Pending JPS558608A (en) | 1978-06-30 | 1978-06-30 | Semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS558608A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02146635A (en) * | 1988-11-29 | 1990-06-05 | Fujitsu Ltd | Parity check circuit |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4852140A (en) * | 1971-10-25 | 1973-07-21 |
-
1978
- 1978-06-30 JP JP7869178A patent/JPS558608A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4852140A (en) * | 1971-10-25 | 1973-07-21 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02146635A (en) * | 1988-11-29 | 1990-06-05 | Fujitsu Ltd | Parity check circuit |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5345120A (en) | Video special effect device | |
KR860002870A (en) | Integrated circuit devices | |
KR840000853A (en) | 2D address device | |
KR850003610A (en) | Semiconductor memory device | |
KR910001777A (en) | Speed memory line memory | |
KR890008836A (en) | Memory device | |
KR840005593A (en) | Monolithic Semiconductor Memory | |
JPS558608A (en) | Semiconductor memory device | |
KR880011795A (en) | Semiconductor memory device | |
DE59307527D1 (en) | Integrated semiconductor memory device | |
JPS57127997A (en) | Semiconductor integrated storage device | |
EP0254065A3 (en) | Address multiplex type semi-conductor memory | |
JPS5376815A (en) | Magnetic recorder/reproducer | |
JPS57130135A (en) | Timing control circuit | |
KR890015602A (en) | Magnetic recording device | |
KR870010440A (en) | Interfacing Control Circuit of CD-ROM Driver | |
JPS5442940A (en) | Start signal regenerating circuit for memory device | |
JPS5443433A (en) | Memory element designation system | |
JPS5525109A (en) | Logic circuit | |
KR940002859A (en) | Light Enable (WE) Buffer Protection Circuit | |
JPS5622292A (en) | Memory element | |
SU430498A1 (en) | RESTORING A CONSTANT COMPONENT | |
JPS5543636A (en) | Digital device | |
JPS5539965A (en) | Data buffer circuit | |
KR940004643A (en) | Dual Port DRAM Device |