JPH02146635A - Parity check circuit - Google Patents

Abstract

PURPOSE:To prevent the undershoot of both address and parity lines and to realize the high density of a memory together with the high speed working by connecting a termination process circuit to both address and parity line connecting lines and making the process circuit serve as an undershoot preventing circuit. CONSTITUTION:A termination process circuit 23 is connected to an address line connecting lines 17 and a parity line connecting line 18 of a parity check circuit 16. Then the circuit 23 serves as an undershoot preventing circuit. Thus the circuit 23 is set into the circuit 16 and the undershoot preventing circuit is substantially set at the termination of an address line 1 and a parity line 4 respectively. Then the undershoot can be prevented from both lines 1 and 4. Then it is not required to occupy the built-in side of a memory element 3 and to improve the built-in density of the element 3 just with use of a single circuit 16 serving as an undershoot preventing circuit.

Description

[Detailed Description of the Invention] [Summary] With regard to a parity check circuit installed on a printed circuit board equipped with a large number of IC memories, the purpose of the present invention is to provide a parity check circuit that also serves as an undershoot prevention circuit to increase the density of the circuit. A termination processing circuit is connected to the address line connection line and the parity line connection line of the circuit, so that it also serves as an undershoot prevention circuit.

[Industrial application field]

The present invention relates to a parity check circuit provided on a printed board equipped with a large number of IC memories.

[Conventional technology]

In conventional printed circuit boards equipped with a large number of IC memories, the second
Driver 2 connected to address line 1 as shown in the figure
and a plurality of memory elements 3 . to which address signals A, (i=1 to n) are supplied from the driver 2 . ..., 3, a parity line 4 branching off the address line 1 from the output side of the driver 2, and a parity generator 5 connected to the parity line 4 and inputting the output of the driver 2. , a parity check circuit 6 is provided in which the far end of the address line 1 from the driver 2 and the far end of the parity line 4 from the parity generator 5 are connected to the input end side, and it is possible to detect defects in the address line 1, defects in the driver 2, Alternatively, the memory element 3 is checked for input defects.

[Problem to be solved by the invention]

In the conventional printed circuit board described above, a parity check circuit 6 is provided in the memory system 10 to take measures against a defect in the address line 1, a defect in the driver 2, or an input defect in the memory element 3. To prevent the undershoot that occurs when supplying the address signal to the memory element 3, either no special measures are taken, or a termination diode is used as a termination near the input terminal of each memory element 3 on the address line 1. Methods such as grounding were used.For this reason, undershoot may occur if no special measures are taken, but undershoot can be prevented if termination is done. However, several termination processing circuits are required for the memory element 3,
There is a problem in that a large area of the printed board is occupied by the termination processing circuit, which prevents higher circuit density.

The present invention has been made in view of the above problems, and the technical problem set to solve the problem is to provide a parity check that doubles as an undershoot prevention circuit to enable higher circuit density. The purpose is to provide circuits.

[Means to solve the problem]

As a specific means for solving the above problems, the present invention provides a driver 2 for an address line 1, as shown in the embodiment drawing of FIG.
In a parity check circuit 16 in which the far end of the parity line 4 and the far end of the parity line 4 from the parity generator 5 are connected to the input side, an address line connection line 17 and a parity line connection line 18 of the parity check circuit 16 are connected to each other.
The termination processing circuit 23 is connected to serve also as an undershoot prevention circuit.

[Effect]

In the present invention, with the above configuration, the termination processing circuit 23 is incorporated into the parity check circuit 16, and an undershoot prevention circuit is substantially provided at the ends of the address line 1 and the parity line 4. 4 undershoot can be prevented. This results in
By providing only one parity check circuit 16 which also serves as an undershoot prevention circuit, it is not necessary to occupy the area on the installation side of the memory element 3, and the memory element 3 can be installed at a high density.

〔Example 〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following, an embodiment of the present invention will be illustrated and described in which a gate circuit is used for the parity checker and a termination processing diode connection circuit is used for the termination processing circuit.

As shown in FIG. 1, the memory system 10 includes a driver 2 connected to an address line 1, and a plurality of memory elements 3. ..., 3, a parity line 4 branching off the address line 1 from the output side of the driver 2, and N connected to the parity line 4 to input the output of the driver 2.
A parity check circuit 1 for undershoot prevention, in which a parity generator 5 consisting of an AND circuit, the far end of the address line 1 from the driver 2, and the far end of the parity line 4 from the parity generator 5' are connected to the input end side.
6 will be provided.

Parity check circuit 16 that also serves as undershoot prevention
is address line connection line 1 to which address line 1 is connected.
Parity line connection line 1 connecting 7 and parity line 4
A parity checker 19 consists of a NAND circuit that connects 8 and 8 to the input end, and the address line connection line 17 is branched and grounded via a termination diode 21, and the parity line connection line 18 is branched and connected to a termination diode. A termination processing circuit 23 is provided which is grounded via 22.

According to such an embodiment, the driver 2 is operated to send an address signal A□ (i=0 to n-1) to each memory element 3.
When transmitting, the undershoot and overshoot that occur on the address line 1 side are suppressed by the termination processing diode 21 of the termination processing circuit 23, and the undershoot and overshoot that occur on the parity line 4 are This is inhibited by the termination processing tie-auto 22 of the processing circuit 23, and stable input to the memory element 3 is performed.

In this embodiment, defects occurring in the memory element 3 due to undershoot when an address signal is input can be prevented by the termination processing circuit 23 provided in the validation check circuit 16 which also serves as undershoot prevention.
A defect in the driver 2, a defect in the input of the memory element 3, etc. can be prevented by a parity checker 19 provided in the parity generator 5 and a parity check circuit 16 which also serves as undershoot prevention.

As a result, by simply providing one validation check circuit 16 that also serves as undershoot prevention in the memory system 10, the area on the side where the memory element is incorporated can be used effectively, reliability can be improved, and the memory element 3 can be efficiently incorporated and the density can be increased.

Furthermore, since undershoot can be prevented, the memory system 10 can operate stably at high speed.

〔Effect of the invention 〕

As described above, in the present invention, the termination processing circuit 23 is connected to the address line connection line 17 and the parity line connection line 18 of the parity check circuit 16, and the termination processing circuit 23 is also used as an undershoot prevention circuit. A termination processing circuit can be provided at the end of the parity line 4, and undershoot between the address line 1 and the parity line 4 can be prevented. Therefore, by providing only one parity check circuit 16 which also serves as undershoot prevention, it is possible to avoid occupying the integrated area of the memory element 3, and it is possible to increase the density of the memory and increase the speed of operation.

23... Termination processing circuit

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing a parity check circuit that also serves as an undershoot prevention circuit according to the present invention, and FIG. 2 is a configuration explanatory diagram showing a memory system having a conventional parity check circuit. 1... Address line 2... Driver 3... Memory element 4... Parity line 5... Parity generator 10... Memory system 16... Parity check circuit 17... Address line connection line 18... Parity line connection line 19... Parity checker 21... Termination processing diode 22... Termination processing diode

Claims (1)

[Claims] A parity check circuit in which the far end of the address line (1) from the driver (2) and the far end of the parity line (4) from the parity generator (5) are connected to the input side. In 16), a termination processing circuit (23) is connected to the address line connection line (17) and the parity line connection line (18) of the parity check circuit (16), so that the terminal processing circuit (23) is also used as an undershoot prevention circuit. Features a parity check circuit.