JPS5585928A - Bus duplex system for clock signal - Google Patents

Bus duplex system for clock signal

Info

Publication number
JPS5585928A
JPS5585928A JP16163878A JP16163878A JPS5585928A JP S5585928 A JPS5585928 A JP S5585928A JP 16163878 A JP16163878 A JP 16163878A JP 16163878 A JP16163878 A JP 16163878A JP S5585928 A JPS5585928 A JP S5585928A
Authority
JP
Japan
Prior art keywords
clock signal
clock
clk8
logical sum
exclusive logical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16163878A
Other languages
Japanese (ja)
Other versions
JPS5822766B2 (en
Inventor
Kazuhiro Sato
Tadao Nozaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53161638A priority Critical patent/JPS5822766B2/en
Publication of JPS5585928A publication Critical patent/JPS5585928A/en
Publication of JPS5822766B2 publication Critical patent/JPS5822766B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)

Abstract

PURPOSE: To increase the reliability of unit, by preventing the extending range for failure effect due to logic degeneration which is a problem in case of DC coupling between elements, through the reception of clock signal with exclusive logical sum circuit.
CONSTITUTION: When initial set is made so that the failure detection circuit DET2 outputs "0" to the C0 terminal and "1" to the C1 terminal, the source clock CLK8 is outputted with the same polarity from the exclusive logical sum gate Gc and inputted to the NAND gates GA, GB, which are selected with C1 signal, and signal is fed to the clock signal bus A6 with the polarity inverted CLK8 from GA only. Since GB normally outputs "1", the clock signal bus B7 is held at "1". On the other hand, the modules 3W5 at the reception side receive the both of the buses A6, B7 at the exclusive logical sum gates G1, G2 and Gn and they can receive the clock with the same polarity as the source clock CLK8.
COPYRIGHT: (C)1980,JPO&Japio
JP53161638A 1978-12-23 1978-12-23 Clock signal bus duplex system Expired JPS5822766B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53161638A JPS5822766B2 (en) 1978-12-23 1978-12-23 Clock signal bus duplex system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53161638A JPS5822766B2 (en) 1978-12-23 1978-12-23 Clock signal bus duplex system

Publications (2)

Publication Number Publication Date
JPS5585928A true JPS5585928A (en) 1980-06-28
JPS5822766B2 JPS5822766B2 (en) 1983-05-11

Family

ID=15738984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53161638A Expired JPS5822766B2 (en) 1978-12-23 1978-12-23 Clock signal bus duplex system

Country Status (1)

Country Link
JP (1) JPS5822766B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60112529A (en) * 1983-11-18 1985-06-19 Electroplating Eng Of Japan Co Loading apparatus
JPS60145134U (en) * 1984-03-06 1985-09-26 東陶機器株式会社 SMC loading device
JPS63218447A (en) * 1987-03-05 1988-09-12 Cmk Corp Supply device for printed-wiring original plate or the like

Also Published As

Publication number Publication date
JPS5822766B2 (en) 1983-05-11

Similar Documents

Publication Publication Date Title
JPS57164636A (en) Control method for transmission system
KR830009695A (en) Arbitration Circuit
JPS5792948A (en) Loop data transmission system
JPS5585928A (en) Bus duplex system for clock signal
DE3465231D1 (en) Single clocked latch circuit
JPS5231629A (en) Data communiction system
JPS5413236A (en) Bus control system
JPS55166749A (en) Decoder circuit
JPS5741069A (en) Inter-frame encoding system
JPS5396606A (en) Switching system
JPS55150025A (en) Information protecting circuit
JPS53111255A (en) Check system for interface control signal
JPS562047A (en) Debugging unit
JPS5396607A (en) Swetching system
JPS53141448A (en) Logical operation circuit
JPS56153469A (en) Computer coupling system
JPS52137233A (en) Computer duplex system
JPS54124947A (en) Error check system of arithmetic circuit
JPS54100234A (en) Common bus system input/output circuit
JPS5642862A (en) Fault detecting system for electronic computer
JPS5676826A (en) Data transfer control system
JPS5755446A (en) Check system for digital transfer data
JPS56138350A (en) Bidirectional and undirectional conversion circuit
JPS5321511A (en) Digital signal processing system
JPS56132645A (en) Check system of input data selection signal for register