JPS5585142A - Semiconductor fail safe logic circuit - Google Patents
Semiconductor fail safe logic circuitInfo
- Publication number
- JPS5585142A JPS5585142A JP15754978A JP15754978A JPS5585142A JP S5585142 A JPS5585142 A JP S5585142A JP 15754978 A JP15754978 A JP 15754978A JP 15754978 A JP15754978 A JP 15754978A JP S5585142 A JPS5585142 A JP S5585142A
- Authority
- JP
- Japan
- Prior art keywords
- constant current
- photo
- voltage
- circuit
- fail safe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/007—Fail-safe circuits
Landscapes
- Logic Circuits (AREA)
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
Abstract
PURPOSE:To obtain the logic circuit having fail safe function by combining the current constant circuit of step type constant current characteristics and the photo coupler, through the use of breakdown phenomenon of junction type FET and constant current diode used. CONSTITUTION:The constant current circuit having step type constant current characteristics using the breakdown phenomenon of FET is constituted with junction type FET's 5, 6, resistors 7, 8, and constant current diodes 9, 11. The constant current circuit controls the current flowing to the light emitting diodes 13, 14 of the photo couplers 10, 12. Further, when the voltage within specific range is fed to the input terminals 1, 2 and 3, 4, stable point is made within active region of the photo transistors 17, 19. When either of photo transistor 17 or 19 does not take stable point within active region, the voltage at the output terminal 18 is closed to the voltage at the power supply terminals 15, 20, allowing to obtain normal output even if one failure is taken place.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15754978A JPS5585142A (en) | 1978-12-22 | 1978-12-22 | Semiconductor fail safe logic circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15754978A JPS5585142A (en) | 1978-12-22 | 1978-12-22 | Semiconductor fail safe logic circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5585142A true JPS5585142A (en) | 1980-06-26 |
Family
ID=15652102
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15754978A Pending JPS5585142A (en) | 1978-12-22 | 1978-12-22 | Semiconductor fail safe logic circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5585142A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2579041A1 (en) * | 1985-03-13 | 1986-09-19 | Jeumont Schneider | LOGIC CIRCUIT GENERATING A MAXIMUM DETERMINED OUTPUT DIRECT CURRENT |
JPS6439119A (en) * | 1987-08-04 | 1989-02-09 | Nec Corp | Logical operation circuit |
JPH0275507U (en) * | 1988-11-29 | 1990-06-08 |
-
1978
- 1978-12-22 JP JP15754978A patent/JPS5585142A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2579041A1 (en) * | 1985-03-13 | 1986-09-19 | Jeumont Schneider | LOGIC CIRCUIT GENERATING A MAXIMUM DETERMINED OUTPUT DIRECT CURRENT |
JPS6439119A (en) * | 1987-08-04 | 1989-02-09 | Nec Corp | Logical operation circuit |
JPH0275507U (en) * | 1988-11-29 | 1990-06-08 |
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