JPS5585024A - Method of fabricating semiconductor device - Google Patents

Method of fabricating semiconductor device

Info

Publication number
JPS5585024A
JPS5585024A JP15976578A JP15976578A JPS5585024A JP S5585024 A JPS5585024 A JP S5585024A JP 15976578 A JP15976578 A JP 15976578A JP 15976578 A JP15976578 A JP 15976578A JP S5585024 A JPS5585024 A JP S5585024A
Authority
JP
Japan
Prior art keywords
impurity
supplied
semiconductor substrates
gas
tube
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15976578A
Other languages
Japanese (ja)
Inventor
Masahiro Ihara
Goro Hagio
Mami Yokozawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP15976578A priority Critical patent/JPS5585024A/en
Publication of JPS5585024A publication Critical patent/JPS5585024A/en
Pending legal-status Critical Current

Links

Landscapes

  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE: To reduce the irregular diffusion of impurity among semiconductor substrates by giving at least one revolution to the impurity gas supplying direction into a tube when diffusion the impurity into a plurality of semiconductor substrates by a tube opening system.
CONSTITUTION: A plurality of semiconductor substrates are disposed in a quartz tube 1, impurity gas is first fed in a direction X, and heat treated for predetermined time. Assuming that the sheet resistances Ps of the substrates 2a, 2b, 2c are PU, PL at the uppermost and lowermost substrate positions with respect to gas stream at this time, it becomes the relationship as designated by a curve A in the graph. When the impurity gas is supplied then in direction Y, the sheet resistance becomes the relationship as designated by a curve B. That is, the irregular sheet resistance when the impurity is supplied in the direction X cancels that when the impurity is supplied in the direction Y each other. The supplying direction may be inverted several times, and this method can be applied for etching, heat treating processes, etc. except for this diffusing treatment.
COPYRIGHT: (C)1980,JPO&Japio
JP15976578A 1978-12-21 1978-12-21 Method of fabricating semiconductor device Pending JPS5585024A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15976578A JPS5585024A (en) 1978-12-21 1978-12-21 Method of fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15976578A JPS5585024A (en) 1978-12-21 1978-12-21 Method of fabricating semiconductor device

Publications (1)

Publication Number Publication Date
JPS5585024A true JPS5585024A (en) 1980-06-26

Family

ID=15700769

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15976578A Pending JPS5585024A (en) 1978-12-21 1978-12-21 Method of fabricating semiconductor device

Country Status (1)

Country Link
JP (1) JPS5585024A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008244088A (en) * 2007-03-27 2008-10-09 Naoetsu Electronics Co Ltd Heat treatment method and heat treatment equipment

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008244088A (en) * 2007-03-27 2008-10-09 Naoetsu Electronics Co Ltd Heat treatment method and heat treatment equipment

Similar Documents

Publication Publication Date Title
JPS57126127A (en) Diffusion treating method for semiconductor wafer
JPS5585024A (en) Method of fabricating semiconductor device
JPS5775431A (en) Formation of pattern
JPS5494869A (en) Production of semiconductor device
JPS5681935A (en) Semiconductor device and its manufacture
JPS56169324A (en) Diffusion of impurity
JPS51113461A (en) A method for manufacturing semiconductor devices
JPH0547685A (en) Method of diffusing impurity to semiconductor wafer
JPS55163838A (en) Manufacturing for semiconductor device
JPS57121234A (en) Plasma processing and device thereof
JPS5599726A (en) Method and device for plasma treatment
JPS5329676A (en) Gas treating method of semiconductor wafers
JPS55105380A (en) Manufacture of semiconductor device
JPS56162829A (en) Manufacture of semiconductor device
JPS5368569A (en) Rough surfaced substrate for impurity diffusion
JPS5361270A (en) Treating method for vapor phase reaction of semiconductor
JPS5272162A (en) Production of semiconductor device
JPS5680129A (en) Manufacture of semiconductor device
JPS57181128A (en) Manufacture of semiconductor device
JPS564285A (en) Manufacture of planar type semiconductor device
JPS5361272A (en) Boron impurity high concentration diffusion method to semiconductor
JPS5643733A (en) Manufacture of semiconductor device
JPS5759322A (en) Manufacture of semiconductor device
JPS5575240A (en) Method of fabricating semiconductor device
JPS53116773A (en) Impurity diffusion method