JPS5580923A - Phase synchronous circuit - Google Patents

Phase synchronous circuit

Info

Publication number
JPS5580923A
JPS5580923A JP15417178A JP15417178A JPS5580923A JP S5580923 A JPS5580923 A JP S5580923A JP 15417178 A JP15417178 A JP 15417178A JP 15417178 A JP15417178 A JP 15417178A JP S5580923 A JPS5580923 A JP S5580923A
Authority
JP
Japan
Prior art keywords
parallel
comparator
phase
input
double
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15417178A
Other languages
Japanese (ja)
Inventor
Takeshi Shima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP15417178A priority Critical patent/JPS5580923A/en
Publication of JPS5580923A publication Critical patent/JPS5580923A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To avoid the backlash by putting the phase comparator featuring a small transition number in parallel to the conventional frequency comparator. CONSTITUTION:In parallel to double input frequency comparator 4, 1/2 dividers 6 and 7 are installed to the input step of double input phase comparator 8. The lock range is magnified double and equivalently at the input step of the divider. The output of two comparators are piled on to each other at the charge pump step or the loop filter step. Thus no discontinuity is caused to the phase comparison range by the parallel distribution of the dividers. As a result, the gain never lowers down for the phase comparator even near the steady point, thus avoiding the backlash without causing any delay to the phase comparison.
JP15417178A 1978-12-15 1978-12-15 Phase synchronous circuit Pending JPS5580923A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15417178A JPS5580923A (en) 1978-12-15 1978-12-15 Phase synchronous circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15417178A JPS5580923A (en) 1978-12-15 1978-12-15 Phase synchronous circuit

Publications (1)

Publication Number Publication Date
JPS5580923A true JPS5580923A (en) 1980-06-18

Family

ID=15578377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15417178A Pending JPS5580923A (en) 1978-12-15 1978-12-15 Phase synchronous circuit

Country Status (1)

Country Link
JP (1) JPS5580923A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293718A (en) * 1988-05-20 1989-11-27 Hitachi Ltd Phase locked loop circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01293718A (en) * 1988-05-20 1989-11-27 Hitachi Ltd Phase locked loop circuit

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