JPS558031A - Semi-conductor device - Google Patents

Semi-conductor device

Info

Publication number
JPS558031A
JPS558031A JP8011378A JP8011378A JPS558031A JP S558031 A JPS558031 A JP S558031A JP 8011378 A JP8011378 A JP 8011378A JP 8011378 A JP8011378 A JP 8011378A JP S558031 A JPS558031 A JP S558031A
Authority
JP
Japan
Prior art keywords
film
wiring
layer
metal
plated metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8011378A
Other languages
Japanese (ja)
Inventor
Masaru Nakamura
Kazuhiro Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8011378A priority Critical patent/JPS558031A/en
Publication of JPS558031A publication Critical patent/JPS558031A/en
Pending legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To prevent line breakage at a connection window section by providing No. 1 metal-silicon compound layer between a semi-conductor base plate and a plated metal and also by providing No. 2 metal-silicon compound layer between the plated metal film and wiring.
CONSTITUTION: A dispersion layer 2 is provided on an Si base plate and a connection window of the layer 2 is provided on an SiO2 film 3 and an Si3N4 film 4. A Pt-Si film 5 and a Cu film 6 are embedded in the window, and an Al-Si wiring 7 and an Si wiring 8 and an Al wiring 9 are piled thereon. These wirings are separated by an SiO2 film 10 and a porous Al2O3 film formed by anodizing process. Further, the Al wiring 9 is covered with a non-porous Al2O3 film 12. In this mechanism, the plated metal film can be completely embedded in level even if there were remarkable difference in elevation of insulation films at the connection window section or scratches on the piled layers of insulation films, and therefore, it is possible to prevent the Al layer 9 from line breakage.
COPYRIGHT: (C)1980,JPO&Japio
JP8011378A 1978-06-30 1978-06-30 Semi-conductor device Pending JPS558031A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8011378A JPS558031A (en) 1978-06-30 1978-06-30 Semi-conductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8011378A JPS558031A (en) 1978-06-30 1978-06-30 Semi-conductor device

Publications (1)

Publication Number Publication Date
JPS558031A true JPS558031A (en) 1980-01-21

Family

ID=13709122

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8011378A Pending JPS558031A (en) 1978-06-30 1978-06-30 Semi-conductor device

Country Status (1)

Country Link
JP (1) JPS558031A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02341A (en) * 1987-02-02 1990-01-05 Seiko Epson Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02341A (en) * 1987-02-02 1990-01-05 Seiko Epson Corp Semiconductor device

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