JPS5571036A - Method of manufacturing integrated circuit - Google Patents

Method of manufacturing integrated circuit

Info

Publication number
JPS5571036A
JPS5571036A JP14533979A JP14533979A JPS5571036A JP S5571036 A JPS5571036 A JP S5571036A JP 14533979 A JP14533979 A JP 14533979A JP 14533979 A JP14533979 A JP 14533979A JP S5571036 A JPS5571036 A JP S5571036A
Authority
JP
Japan
Prior art keywords
integrated circuit
manufacturing integrated
manufacturing
circuit
integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14533979A
Other languages
English (en)
Other versions
JPH0252422B2 (ja
Inventor
Goodon Fuareru Maikeru
Toomasu Masutoroianni Saru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of JPS5571036A publication Critical patent/JPS5571036A/ja
Publication of JPH0252422B2 publication Critical patent/JPH0252422B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Bipolar Transistors (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
JP14533979A 1978-11-13 1979-11-09 Method of manufacturing integrated circuit Granted JPS5571036A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/960,143 US4199380A (en) 1978-11-13 1978-11-13 Integrated circuit method

Publications (2)

Publication Number Publication Date
JPS5571036A true JPS5571036A (en) 1980-05-28
JPH0252422B2 JPH0252422B2 (ja) 1990-11-13

Family

ID=25502843

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14533979A Granted JPS5571036A (en) 1978-11-13 1979-11-09 Method of manufacturing integrated circuit

Country Status (3)

Country Link
US (1) US4199380A (ja)
JP (1) JPS5571036A (ja)
NL (1) NL7908310A (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS575358A (en) * 1980-06-13 1982-01-12 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS57104240A (en) * 1980-12-22 1982-06-29 Nec Corp Semiconductor device
JPS57149770A (en) * 1981-03-11 1982-09-16 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS59161067A (ja) * 1983-03-04 1984-09-11 Hitachi Micro Comput Eng Ltd バイポ−ラ型半導体装置の製造方法
JP2007501511A (ja) * 2003-08-02 2007-01-25 ゼテックス・ピーエルシー 低飽和電圧のバイポーラトランジスタ

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5852339B2 (ja) * 1979-03-20 1983-11-22 富士通株式会社 半導体装置の製造方法
JPS57139965A (en) * 1981-02-24 1982-08-30 Toshiba Corp Manufacture of semiconductor device
JPS57194572A (en) * 1981-05-27 1982-11-30 Clarion Co Ltd Semiconductor device and manufacture thereof
US4465528A (en) * 1981-07-15 1984-08-14 Fujitsu Limited Method of producing a walled emitter semiconductor device
EP0071665B1 (de) * 1981-08-08 1986-04-16 Deutsche ITT Industries GmbH Verfahren zum Herstellen einer monolithisch integrierten Festkörperschaltung mit mindestens einem bipolaren Planartransistor
US4443931A (en) * 1982-06-28 1984-04-24 General Electric Company Method of fabricating a semiconductor device with a base region having a deep portion
US4498227A (en) * 1983-07-05 1985-02-12 Fairchild Camera & Instrument Corporation Wafer fabrication by implanting through protective layer
US4630096A (en) * 1984-05-30 1986-12-16 Motorola, Inc. High density IC module assembly
US4583282A (en) * 1984-09-14 1986-04-22 Motorola, Inc. Process for self-aligned buried layer, field guard, and isolation
US4573257A (en) * 1984-09-14 1986-03-04 Motorola, Inc. Method of forming self-aligned implanted channel-stop and buried layer utilizing non-single crystal alignment key
US4574469A (en) * 1984-09-14 1986-03-11 Motorola, Inc. Process for self-aligned buried layer, channel-stop, and isolation
JPS61222137A (ja) * 1985-03-06 1986-10-02 Sharp Corp チップ識別用凹凸パターン形成方法
JPS63114261A (ja) * 1986-09-11 1988-05-19 フェアチャイルド　セミコンダクタ　コーポレーション トランジスタ用の自己整合型ベース分路
US4883772A (en) * 1986-09-11 1989-11-28 National Semiconductor Corporation Process for making a self-aligned silicide shunt
IT1231913B (it) * 1987-10-23 1992-01-15 Sgs Microelettronica Spa Procedimento di fabbricazione di transistori ad alta frequenza.
US5338695A (en) * 1992-11-24 1994-08-16 National Semiconductor Corporation Making walled emitter bipolar transistor with reduced base narrowing

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS507422A (ja) * 1973-05-18 1975-01-25
JPS5010579A (ja) * 1973-05-25 1975-02-03
JPS5119484A (en) * 1974-08-09 1976-02-16 Hitachi Ltd Handotaisochito sonoseizohoho
JPS5248978A (en) * 1975-10-17 1977-04-19 Hitachi Ltd Process for production of semiconductor device
JPS5278387A (en) * 1975-12-24 1977-07-01 Fujitsu Ltd Production of semiconductor device
JPS52114280A (en) * 1976-03-22 1977-09-24 Nec Corp Bipolar type transistor

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079402A (en) * 1973-07-09 1978-03-14 National Semiconductor Corporation Zener diode incorporating an ion implanted layer establishing the breakdown point below the surface
US4060427A (en) * 1976-04-05 1977-11-29 Ibm Corporation Method of forming an integrated circuit region through the combination of ion implantation and diffusion steps
US4066473A (en) * 1976-07-15 1978-01-03 Fairchild Camera And Instrument Corporation Method of fabricating high-gain transistors
US4110125A (en) * 1977-03-03 1978-08-29 International Business Machines Corporation Method for fabricating semiconductor devices
US4111726A (en) * 1977-04-01 1978-09-05 Burroughs Corporation Bipolar integrated circuit process by separately forming active and inactive base regions
US4135954A (en) * 1977-07-12 1979-01-23 International Business Machines Corporation Method for fabricating self-aligned semiconductor devices utilizing selectively etchable masking layers
US4131497A (en) * 1977-07-12 1978-12-26 International Business Machines Corporation Method of manufacturing self-aligned semiconductor devices
US4118250A (en) * 1977-12-30 1978-10-03 International Business Machines Corporation Process for producing integrated circuit devices by ion implantation
US4155778A (en) * 1977-12-30 1979-05-22 International Business Machines Corporation Forming semiconductor devices having ion implanted and diffused regions

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS507422A (ja) * 1973-05-18 1975-01-25
JPS5010579A (ja) * 1973-05-25 1975-02-03
JPS5119484A (en) * 1974-08-09 1976-02-16 Hitachi Ltd Handotaisochito sonoseizohoho
JPS5248978A (en) * 1975-10-17 1977-04-19 Hitachi Ltd Process for production of semiconductor device
JPS5278387A (en) * 1975-12-24 1977-07-01 Fujitsu Ltd Production of semiconductor device
JPS52114280A (en) * 1976-03-22 1977-09-24 Nec Corp Bipolar type transistor

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS575358A (en) * 1980-06-13 1982-01-12 Fujitsu Ltd Semiconductor device and manufacture thereof
JPS57104240A (en) * 1980-12-22 1982-06-29 Nec Corp Semiconductor device
JPS57149770A (en) * 1981-03-11 1982-09-16 Mitsubishi Electric Corp Manufacture of semiconductor device
JPS59161067A (ja) * 1983-03-04 1984-09-11 Hitachi Micro Comput Eng Ltd バイポ−ラ型半導体装置の製造方法
JP2007501511A (ja) * 2003-08-02 2007-01-25 ゼテックス・ピーエルシー 低飽和電圧のバイポーラトランジスタ

Also Published As

Publication number Publication date
NL7908310A (nl) 1980-05-16
JPH0252422B2 (ja) 1990-11-13
US4199380A (en) 1980-04-22

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