JPS5570996A - Dynamic memory control system - Google Patents

Dynamic memory control system

Info

Publication number
JPS5570996A
JPS5570996A JP14424378A JP14424378A JPS5570996A JP S5570996 A JPS5570996 A JP S5570996A JP 14424378 A JP14424378 A JP 14424378A JP 14424378 A JP14424378 A JP 14424378A JP S5570996 A JPS5570996 A JP S5570996A
Authority
JP
Japan
Prior art keywords
output
circuit
time
ambient temperature
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14424378A
Other languages
Japanese (ja)
Inventor
Kiyohiko Kobayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP14424378A priority Critical patent/JPS5570996A/en
Publication of JPS5570996A publication Critical patent/JPS5570996A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G11C19/282—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements with charge storage in a depletion layer, i.e. charge coupled devices [CCD]

Abstract

PURPOSE:To reduce the power consumption, by determining the dynamic memory operation frequency at standby corresponding to the ambient temperature at that time. CONSTITUTION:At standby mode, the signal inputted to the timing signal generating circuit 10 is selected from the output of the pulse oscillator 9 to the output of the frequency divider 8, the ambient temperature of CCD memory is read in at the sensor 4 and given to the conversion table 6 with A/D conversion 5, and the frequency dividing value to generate the minimum operation frequency of CCD memory to the ambient temperature at that time is set to the prescaler 7 from the table 6. The frequency divider 8 counts the output a of the oscillator 9 with this set value, the frequency dividing output is delivered to the circuit 10 every time reaching the set value, and the output of the circuit 10 drives the unit 3. Further, the circuit 10 alters the set value of the prescaler every given time.
JP14424378A 1978-11-24 1978-11-24 Dynamic memory control system Pending JPS5570996A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14424378A JPS5570996A (en) 1978-11-24 1978-11-24 Dynamic memory control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14424378A JPS5570996A (en) 1978-11-24 1978-11-24 Dynamic memory control system

Publications (1)

Publication Number Publication Date
JPS5570996A true JPS5570996A (en) 1980-05-28

Family

ID=15357564

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14424378A Pending JPS5570996A (en) 1978-11-24 1978-11-24 Dynamic memory control system

Country Status (1)

Country Link
JP (1) JPS5570996A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120216057A1 (en) * 2008-08-11 2012-08-23 International Business Machines Corporation Selective Power Reduction of Memory Hardware

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120216057A1 (en) * 2008-08-11 2012-08-23 International Business Machines Corporation Selective Power Reduction of Memory Hardware
US8364995B2 (en) * 2008-08-11 2013-01-29 International Business Machines Corporation Selective power reduction of memory hardware

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