JPS5570137A - Program reservation device - Google Patents
Program reservation deviceInfo
- Publication number
- JPS5570137A JPS5570137A JP14371678A JP14371678A JPS5570137A JP S5570137 A JPS5570137 A JP S5570137A JP 14371678 A JP14371678 A JP 14371678A JP 14371678 A JP14371678 A JP 14371678A JP S5570137 A JPS5570137 A JP S5570137A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- cancel
- information
- circuit
- channel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Electric Clocks (AREA)
- Circuits Of Receivers In General (AREA)
Abstract
PURPOSE:To secure easy-to-understand the reservation cancel and thus to improve the operation for the subsequent actions in case the reservation information of the memory is cancelled, by giving the cancel command to the reservation information to the memory and furthermore displaying the real time when the cancel is released. CONSTITUTION:The information to designate the channel to be selected plus the time information for the channel selection are written for memorization into memory 11 possessing plural number of addresses. Then the memorized information are read out to give the control to channel selection circuit 3, and tuner 2 of the receiver is set to the reserved channel. In case the channel selection and time information memorized in memory 11 are cancelled, the memory address to be cancelled is designated via writing address switch circuit 12, and then the fixed clear pulse is generated through cancel signal generator circuit 15 to clear the contents of memory 11. Then the displays are erased at channel display circuit 5, day/date display unit 29 and time display circuit 30 each, and thus the cancel order is erased. After this, the present real time is displayed at circuit 30 when the first command input is applied.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14371678A JPS5570137A (en) | 1978-11-20 | 1978-11-20 | Program reservation device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14371678A JPS5570137A (en) | 1978-11-20 | 1978-11-20 | Program reservation device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5570137A true JPS5570137A (en) | 1980-05-27 |
Family
ID=15345316
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14371678A Pending JPS5570137A (en) | 1978-11-20 | 1978-11-20 | Program reservation device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5570137A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58184870A (en) * | 1982-04-22 | 1983-10-28 | Murata Giken Kk | Facsimile multiple address device |
JPS58171599U (en) * | 1982-05-11 | 1983-11-16 | トヨタ自動車株式会社 | Vehicle traffic information listening device |
JPH0269791U (en) * | 1988-11-16 | 1990-05-28 |
-
1978
- 1978-11-20 JP JP14371678A patent/JPS5570137A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58184870A (en) * | 1982-04-22 | 1983-10-28 | Murata Giken Kk | Facsimile multiple address device |
JPH0115222B2 (en) * | 1982-04-22 | 1989-03-16 | Murata Machinery Ltd | |
JPS58171599U (en) * | 1982-05-11 | 1983-11-16 | トヨタ自動車株式会社 | Vehicle traffic information listening device |
JPH0269791U (en) * | 1988-11-16 | 1990-05-28 |
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