JPS556611A - Logical controller - Google Patents

Logical controller

Info

Publication number
JPS556611A
JPS556611A JP7800278A JP7800278A JPS556611A JP S556611 A JPS556611 A JP S556611A JP 7800278 A JP7800278 A JP 7800278A JP 7800278 A JP7800278 A JP 7800278A JP S556611 A JPS556611 A JP S556611A
Authority
JP
Japan
Prior art keywords
computer
computers
supplied
signals
controller
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7800278A
Other languages
Japanese (ja)
Other versions
JPS6029426B2 (en
Inventor
Sumio Omura
Eiichi Toyoda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP7800278A priority Critical patent/JPS6029426B2/en
Publication of JPS556611A publication Critical patent/JPS556611A/en
Publication of JPS6029426B2 publication Critical patent/JPS6029426B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Multi Processors (AREA)

Abstract

PURPOSE: To obtain a logical controllers with control functions allotted to three computers or more sequentially connected in a loop via signal lines.
CONSTITUTION: For application to an automatic operating unit, three computers 11 to 13 are provided and each computer, a microcomputer, consists of an arithmetic processing circuit, memory circuit and input-output circuit. The 1st computer 11, in charge of the processing of input signals, processes signals from units 71 and 72 to calculate an operation speed and desired speed, which are supplied to the 2nd computer 12; the 2nd computer 12 calcultes the optimum acceleration, which is supplied to controller 74. The 3rd computer 13 obtains required signals from the 2nd computer 12 to generate a brake control signal through an arithmetic process and then supplies the signal to brake controller 75. The output of the 3rd computer 13 is further transmitted to the 1st computer 11, where the calculation result of its own is checked.
COPYRIGHT: (C)1980,JPO&Japio
JP7800278A 1978-06-29 1978-06-29 Vehicle control device Expired JPS6029426B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7800278A JPS6029426B2 (en) 1978-06-29 1978-06-29 Vehicle control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7800278A JPS6029426B2 (en) 1978-06-29 1978-06-29 Vehicle control device

Publications (2)

Publication Number Publication Date
JPS556611A true JPS556611A (en) 1980-01-18
JPS6029426B2 JPS6029426B2 (en) 1985-07-10

Family

ID=13649582

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7800278A Expired JPS6029426B2 (en) 1978-06-29 1978-06-29 Vehicle control device

Country Status (1)

Country Link
JP (1) JPS6029426B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5279036A (en) * 1975-12-24 1977-07-02 Sunstar Inc Dentifrice compound

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5279036A (en) * 1975-12-24 1977-07-02 Sunstar Inc Dentifrice compound
JPS556610B2 (en) * 1975-12-24 1980-02-18

Also Published As

Publication number Publication date
JPS6029426B2 (en) 1985-07-10

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