JPS5552596A - Shift register circuit - Google Patents
Shift register circuitInfo
- Publication number
- JPS5552596A JPS5552596A JP12587078A JP12587078A JPS5552596A JP S5552596 A JPS5552596 A JP S5552596A JP 12587078 A JP12587078 A JP 12587078A JP 12587078 A JP12587078 A JP 12587078A JP S5552596 A JPS5552596 A JP S5552596A
- Authority
- JP
- Japan
- Prior art keywords
- clock signal
- fets
- stage
- those
- registers
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
- G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
- G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Shift Register Type Memory (AREA)
Abstract
PURPOSE:To simplify circuit constitution by reducing a chip size in case of IC-implementation by driving cascaded one-bit shift registers by a single clock signal. CONSTITUTION:One-bit shift registers 201-208 are cascaded and supplied with single clock signal phi in parallel, and an output from final-stage register 208 is fed back to initialstage register 201 through control gate logic circuit 21 supplied with a control signal. Those registers 201-208 are provided with a circuit of N-type FETs 25 and 26 connected in series between power supply Vss and output terminal 24 and that of P-type FETs 27 and 28 connected in series between power supply VDD and output terminal 24. Gates of those FETs 26 and 27 are connected for input terminal 29, and those of FETs 25 and 28 are also connected to obtain an input termianl for clock signal phi, so that prior-stage and post-stage clock inverters 22 and 23 will be constituted. Then, registers 201-208 are driven by single clock signal phi.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12587078A JPS5552596A (en) | 1978-10-13 | 1978-10-13 | Shift register circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12587078A JPS5552596A (en) | 1978-10-13 | 1978-10-13 | Shift register circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5552596A true JPS5552596A (en) | 1980-04-17 |
Family
ID=14920960
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12587078A Pending JPS5552596A (en) | 1978-10-13 | 1978-10-13 | Shift register circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5552596A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07239676A (en) * | 1994-02-28 | 1995-09-12 | Nec Corp | Scanning circuit |
JPH08263013A (en) * | 1995-03-23 | 1996-10-11 | Nec Corp | Driving circuit |
-
1978
- 1978-10-13 JP JP12587078A patent/JPS5552596A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07239676A (en) * | 1994-02-28 | 1995-09-12 | Nec Corp | Scanning circuit |
JPH08263013A (en) * | 1995-03-23 | 1996-10-11 | Nec Corp | Driving circuit |
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