JPS5552024A - Light modulator control system - Google Patents

Light modulator control system

Info

Publication number
JPS5552024A
JPS5552024A JP12463478A JP12463478A JPS5552024A JP S5552024 A JPS5552024 A JP S5552024A JP 12463478 A JP12463478 A JP 12463478A JP 12463478 A JP12463478 A JP 12463478A JP S5552024 A JPS5552024 A JP S5552024A
Authority
JP
Japan
Prior art keywords
signal
output
digital modulating
carrier
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12463478A
Other languages
Japanese (ja)
Inventor
Tomohisa Mikami
Fumitaka Abe
Fumio Sakurai
Tadashi Matsuda
Takayuki Kokai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP12463478A priority Critical patent/JPS5552024A/en
Publication of JPS5552024A publication Critical patent/JPS5552024A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To perform modulation with an extremely simple circuit by analogically adding the digital modulating signal of a crest value 1/2 the output obtained by gating the carrier signal with the digital modulating signal by logic elements to said output.
CONSTITUTION: The carrier signal S2 and digital modulating signal S0 are inputted to a NAND circuit 10 through buffer amplifiers 8, 9 respectively. From the NAND circuit 10, the carrier signal S2 is outputted in an inverted state only in the period when the digital modulating signal S0 is high level, whereby the gate output signal S4 is obtained. This gate output signal S4 is applied to an output resistance 12 via resistor 11 and on the other hand, the digital modulating signal S0 is applied to an output resistor 12 via resistor 13 having the resistance value twice the resistor 11. Hence, the signal S4 is added to the digital modulating signal S5 having the crest value 1/2 the signal S4, whereby the modulating carrier signal S1 having been removed of the carrier components is obtained. In this way, the modulation may be accomplished with the extremely simple circuits.
COPYRIGHT: (C)1980,JPO&Japio
JP12463478A 1978-10-12 1978-10-12 Light modulator control system Pending JPS5552024A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12463478A JPS5552024A (en) 1978-10-12 1978-10-12 Light modulator control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12463478A JPS5552024A (en) 1978-10-12 1978-10-12 Light modulator control system

Publications (1)

Publication Number Publication Date
JPS5552024A true JPS5552024A (en) 1980-04-16

Family

ID=14890261

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12463478A Pending JPS5552024A (en) 1978-10-12 1978-10-12 Light modulator control system

Country Status (1)

Country Link
JP (1) JPS5552024A (en)

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