JPS5544248A - Signal delay circuit - Google Patents

Signal delay circuit

Info

Publication number
JPS5544248A
JPS5544248A JP11709778A JP11709778A JPS5544248A JP S5544248 A JPS5544248 A JP S5544248A JP 11709778 A JP11709778 A JP 11709778A JP 11709778 A JP11709778 A JP 11709778A JP S5544248 A JPS5544248 A JP S5544248A
Authority
JP
Japan
Prior art keywords
delay time
transistor
transistors
operated
tplh
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11709778A
Other languages
Japanese (ja)
Inventor
Chiaki Katsumi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP11709778A priority Critical patent/JPS5544248A/en
Publication of JPS5544248A publication Critical patent/JPS5544248A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electronic Switches (AREA)

Abstract

PURPOSE:To make easy circuit integration, by using IIL composing PNP transistor operated as current source and PNP transistor operated as inverter. CONSTITUTION:The transistors 12-15 are NPN transistor operated as injector and the transistors 8-11 are NPN transistors operated as inverter. When the input signal A fed to the base terminal 16 of the first stage transistor 8 is at ''L'' changed from ''L'' to ''H'', the transistor 8 is ON B at the time point elapsed by delay time tPHL, and the transistor 9 is OFF at the time elapsed by delay time tPLH. The third stage and fourth stage transistors 10 and 11 are respectively ON C and OFF D at the delay time tPLH, and at the output 17, the output signal is obtained delayed by the delay time 2(tPHL+tPLH) in phase with the input signal. This delay time can arbitrarily be set by controlling the number of stages of inverters and supply power.
JP11709778A 1978-09-22 1978-09-22 Signal delay circuit Pending JPS5544248A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11709778A JPS5544248A (en) 1978-09-22 1978-09-22 Signal delay circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11709778A JPS5544248A (en) 1978-09-22 1978-09-22 Signal delay circuit

Publications (1)

Publication Number Publication Date
JPS5544248A true JPS5544248A (en) 1980-03-28

Family

ID=14703314

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11709778A Pending JPS5544248A (en) 1978-09-22 1978-09-22 Signal delay circuit

Country Status (1)

Country Link
JP (1) JPS5544248A (en)

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