JPS564931A - Driving circuit for active element - Google Patents

Driving circuit for active element

Info

Publication number
JPS564931A
JPS564931A JP8118279A JP8118279A JPS564931A JP S564931 A JPS564931 A JP S564931A JP 8118279 A JP8118279 A JP 8118279A JP 8118279 A JP8118279 A JP 8118279A JP S564931 A JPS564931 A JP S564931A
Authority
JP
Japan
Prior art keywords
voltage
signal
level
input
vcc
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8118279A
Other languages
Japanese (ja)
Inventor
Akio Tokuge
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Pioneer Corp
Original Assignee
Pioneer Electronic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Pioneer Electronic Corp filed Critical Pioneer Electronic Corp
Priority to JP8118279A priority Critical patent/JPS564931A/en
Publication of JPS564931A publication Critical patent/JPS564931A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/02—Shaping pulses by amplifying
    • H03K5/023—Shaping pulses by amplifying using field effect transistors

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To make it possible to generate a driving signal high in level without using two electric power sources by receiving an input signal that is nearly equal to an electric power voltage and then by generating and superposing a DC voltage, corresponding to the mean value of the input signal, upon the input signal. CONSTITUTION:An input signal is input to the circuit, consisting of NPN and PNP transistor TRQ1, Q2, etc., to output SEPP output signal es from this circuit. Signal es is supplied to the level shifting circuit composed of capacitor C and resistance R1 and its output signal eg is input to the gate of switching FETQ3. Circuit CR1 generates DC voltage Ec corresponding to the mean value of signal es and it is stored in capacitor C. The voltage of output signal eg of the level shifting circuit is voltage Ec when the input signal is at level zero and level Vcc is superposed upon voltage Ec when the input is at the level of power voltage Vcc, so that a level-shifted bootstrap output can be obtained. As the source electric power source of FETQ3, voltage Vcc is used and the output signal varies from voltage Ec to Ec+Vcc.
JP8118279A 1979-06-27 1979-06-27 Driving circuit for active element Pending JPS564931A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8118279A JPS564931A (en) 1979-06-27 1979-06-27 Driving circuit for active element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8118279A JPS564931A (en) 1979-06-27 1979-06-27 Driving circuit for active element

Publications (1)

Publication Number Publication Date
JPS564931A true JPS564931A (en) 1981-01-19

Family

ID=13739322

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8118279A Pending JPS564931A (en) 1979-06-27 1979-06-27 Driving circuit for active element

Country Status (1)

Country Link
JP (1) JPS564931A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS604037U (en) * 1983-06-22 1985-01-12 ヤマハ株式会社 MOS-FET drive circuit for power amplification
DE3629383A1 (en) * 1985-09-10 1987-03-12 Sgs Microelettronica Spa CIRCUIT ARRANGEMENT WITH A CHARGE PUMP FOR DRIVING N-CHANNEL MOS TRANSISTORS
JPH0372713A (en) * 1989-08-11 1991-03-27 Nippon Telegr & Teleph Corp <Ntt> Mosfet driving circuit

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5238852A (en) * 1975-09-22 1977-03-25 Seiko Instr & Electronics Ltd Level shift circuit
JPS5457857A (en) * 1977-09-26 1979-05-10 Philips Nv Buffer circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5238852A (en) * 1975-09-22 1977-03-25 Seiko Instr & Electronics Ltd Level shift circuit
JPS5457857A (en) * 1977-09-26 1979-05-10 Philips Nv Buffer circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS604037U (en) * 1983-06-22 1985-01-12 ヤマハ株式会社 MOS-FET drive circuit for power amplification
DE3629383A1 (en) * 1985-09-10 1987-03-12 Sgs Microelettronica Spa CIRCUIT ARRANGEMENT WITH A CHARGE PUMP FOR DRIVING N-CHANNEL MOS TRANSISTORS
DE3629383C2 (en) * 1985-09-10 1995-12-21 Sgs Microelettronica Spa Circuit arrangement with a charge pump for driving N-channel MOS transistors
JPH0372713A (en) * 1989-08-11 1991-03-27 Nippon Telegr & Teleph Corp <Ntt> Mosfet driving circuit

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