JPS5541547A - Diagnosis system of logical operation circuit - Google Patents

Diagnosis system of logical operation circuit

Info

Publication number
JPS5541547A
JPS5541547A JP11465978A JP11465978A JPS5541547A JP S5541547 A JPS5541547 A JP S5541547A JP 11465978 A JP11465978 A JP 11465978A JP 11465978 A JP11465978 A JP 11465978A JP S5541547 A JPS5541547 A JP S5541547A
Authority
JP
Japan
Prior art keywords
circuit
logical operation
timing signal
operation circuit
control signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11465978A
Other languages
Japanese (ja)
Inventor
Yoshitoshi Tsuji
Yoshihiko Kadowaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11465978A priority Critical patent/JPS5541547A/en
Publication of JPS5541547A publication Critical patent/JPS5541547A/en
Pending legal-status Critical Current

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  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To detect surely a disconnection fault, etc., of the terminal resistance of a logical operation circuit by making the phase of the timing signal of a part of the logical operation circuit different from that at a normal operation time of the logical operation circuit.
CONSTITUTION: A control circuit is constituted by inverter 6, AND circuits 7 and 8 and OR circuit 9, and timing signal TPO or TP2 is supplied to AND circuit 1 according to the level of control signal TEST. In case that control signal TEST is level "0", timing signal TPO is supplied to AND circuit 1 to perform a normal diagnosis. When disconnection, etc., of terminal resistance 3 of flip flop 2 are diagnosed, control signal TEST is set to "1". As a result, timing signal TP2 obtained by delaying timing signal TP2 is applied to trigger input T of flip flop 2.
COPYRIGHT: (C)1980,JPO&Japio
JP11465978A 1978-09-20 1978-09-20 Diagnosis system of logical operation circuit Pending JPS5541547A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11465978A JPS5541547A (en) 1978-09-20 1978-09-20 Diagnosis system of logical operation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11465978A JPS5541547A (en) 1978-09-20 1978-09-20 Diagnosis system of logical operation circuit

Publications (1)

Publication Number Publication Date
JPS5541547A true JPS5541547A (en) 1980-03-24

Family

ID=14643338

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11465978A Pending JPS5541547A (en) 1978-09-20 1978-09-20 Diagnosis system of logical operation circuit

Country Status (1)

Country Link
JP (1) JPS5541547A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015727A (en) * 1983-07-05 1985-01-26 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション System clock controller

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6015727A (en) * 1983-07-05 1985-01-26 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション System clock controller
JPH0418329B2 (en) * 1983-07-05 1992-03-27 Intaanashonaru Bijinesu Mashiinzu Corp

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