JPS5537685A - Data input system - Google Patents

Data input system

Info

Publication number
JPS5537685A
JPS5537685A JP11116978A JP11116978A JPS5537685A JP S5537685 A JPS5537685 A JP S5537685A JP 11116978 A JP11116978 A JP 11116978A JP 11116978 A JP11116978 A JP 11116978A JP S5537685 A JPS5537685 A JP S5537685A
Authority
JP
Japan
Prior art keywords
data
input
signal
signals
multiplexer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11116978A
Other languages
Japanese (ja)
Inventor
Takayoshi Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP11116978A priority Critical patent/JPS5537685A/en
Publication of JPS5537685A publication Critical patent/JPS5537685A/en
Pending legal-status Critical Current

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  • Microcomputers (AREA)

Abstract

PURPOSE: To make it possible to select required data from several different data easily and inexpensively and then to input it, by reading input data after output an input data selective signal in input instruction execution corresponding to an input instruction.
CONSTITUTION: A function of outputting several input data selective signals is provided and in input instruction execution, input data selective signals S1 and S2 are outputted which correspond to an input instruction. The moment those signals are inputted to multiplexer 2 as selective signals for multiplexer 2, data A and B are transmitted from multiplexer 2 to the input port of data processor 1 corresponding to the signals. Data processor 1 is provided with two input instructions READ1 and READ2. When READ1 is executed, signal S1 is outputted and data A is read into input register R. Then, signal S1 is reset. When READ2 is executed, on the other hand, signal S2 is outputted and data B is read. Therefore, required data can selectively be inputted.
COPYRIGHT: (C)1980,JPO&Japio
JP11116978A 1978-09-08 1978-09-08 Data input system Pending JPS5537685A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11116978A JPS5537685A (en) 1978-09-08 1978-09-08 Data input system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11116978A JPS5537685A (en) 1978-09-08 1978-09-08 Data input system

Publications (1)

Publication Number Publication Date
JPS5537685A true JPS5537685A (en) 1980-03-15

Family

ID=14554220

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11116978A Pending JPS5537685A (en) 1978-09-08 1978-09-08 Data input system

Country Status (1)

Country Link
JP (1) JPS5537685A (en)

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