JPS5537030A - Analogue switch circuit - Google Patents
Analogue switch circuitInfo
- Publication number
- JPS5537030A JPS5537030A JP10989878A JP10989878A JPS5537030A JP S5537030 A JPS5537030 A JP S5537030A JP 10989878 A JP10989878 A JP 10989878A JP 10989878 A JP10989878 A JP 10989878A JP S5537030 A JPS5537030 A JP S5537030A
- Authority
- JP
- Japan
- Prior art keywords
- current
- input
- fet
- output current
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Landscapes
- Electronic Switches (AREA)
Abstract
PURPOSE:To minimize the current flowing through the switching element and prevent the generation of distortion without deteriorating S/N by separating input current and output current flowing through FET in circuit. CONSTITUTION:The return resistance Ro is provided between the inverting input and output. FET 2 ON and OFF controlled by a predetermined signal is provided between the inverting input of the operational amplifier A1 earthed non-inverting input and a predetermined input signal Vi. The current i1 corresponding to the input signal vi is impressed to the input, and the output current io is supplied to FET 2 by using the current converting means 10 guiding out the output current of k.i1 (k is a constant smaller than 1). Accordingly, the output current passing through FET 2 and the input current if can be separated in circuit.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10989878A JPS5537030A (en) | 1978-09-07 | 1978-09-07 | Analogue switch circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10989878A JPS5537030A (en) | 1978-09-07 | 1978-09-07 | Analogue switch circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5537030A true JPS5537030A (en) | 1980-03-14 |
Family
ID=14521949
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10989878A Pending JPS5537030A (en) | 1978-09-07 | 1978-09-07 | Analogue switch circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5537030A (en) |
-
1978
- 1978-09-07 JP JP10989878A patent/JPS5537030A/en active Pending
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