JPS5523530A - Display unit of sequence controller - Google Patents

Display unit of sequence controller

Info

Publication number
JPS5523530A
JPS5523530A JP9480878A JP9480878A JPS5523530A JP S5523530 A JPS5523530 A JP S5523530A JP 9480878 A JP9480878 A JP 9480878A JP 9480878 A JP9480878 A JP 9480878A JP S5523530 A JPS5523530 A JP S5523530A
Authority
JP
Japan
Prior art keywords
address
contents
circuit
memory
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9480878A
Other languages
Japanese (ja)
Inventor
Hiroki Daigo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
KOYO DENSHI KOGYO KK
Koyo Electronics Industries Co Ltd
Original Assignee
KOYO DENSHI KOGYO KK
Koyo Electronics Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by KOYO DENSHI KOGYO KK, Koyo Electronics Industries Co Ltd filed Critical KOYO DENSHI KOGYO KK
Priority to JP9480878A priority Critical patent/JPS5523530A/en
Publication of JPS5523530A publication Critical patent/JPS5523530A/en
Pending legal-status Critical Current

Links

Landscapes

  • Programmable Controllers (AREA)

Abstract

PURPOSE: To make it possible to display contents of input, output and operation memories even in a sequence controller operating time by selecting the address of a signal, which should be monitored, by a setting equipment.
CONSTITUTION: Contents of program memory 3 are read out seccessively from zero address 0 to maximum address n at the oscillation period of oscillator 1 according to contents of program counter 2, and contents of instruction part OP are sent to operation part 4 through instruction bus 14, and contents of address part Ad are transmitted to input part 5, output part 6 and operation memory 7 as the operation result through address bus 15. When the address of setting epuipment 9 which sets an address to be monitored and the address read out from memory 3 through bus 15 agree with each other, coincidence circuit 8 sends a signal to memory circuit 10; and since circuit 19 stores the current signal stage of input data line 12 and output data line 13, circuit 10 lights display epuipment 11 when signals from circuit 8 exist.
COPYRIGHT: (C)1980,JPO&Japio
JP9480878A 1978-08-03 1978-08-03 Display unit of sequence controller Pending JPS5523530A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9480878A JPS5523530A (en) 1978-08-03 1978-08-03 Display unit of sequence controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9480878A JPS5523530A (en) 1978-08-03 1978-08-03 Display unit of sequence controller

Publications (1)

Publication Number Publication Date
JPS5523530A true JPS5523530A (en) 1980-02-20

Family

ID=14120347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9480878A Pending JPS5523530A (en) 1978-08-03 1978-08-03 Display unit of sequence controller

Country Status (1)

Country Link
JP (1) JPS5523530A (en)

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