JPS5518761A - Test pattern generator - Google Patents

Test pattern generator

Info

Publication number
JPS5518761A
JPS5518761A JP9160978A JP9160978A JPS5518761A JP S5518761 A JPS5518761 A JP S5518761A JP 9160978 A JP9160978 A JP 9160978A JP 9160978 A JP9160978 A JP 9160978A JP S5518761 A JPS5518761 A JP S5518761A
Authority
JP
Japan
Prior art keywords
information
block
test pattern
address
jump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9160978A
Other languages
Japanese (ja)
Inventor
Shigeki Katsumi
Sadao Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9160978A priority Critical patent/JPS5518761A/en
Publication of JPS5518761A publication Critical patent/JPS5518761A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To make it possible to generate identical patterns as many as repetitive operations when testing the logic of the integrated circuit of an electronic watch, etc., by making it possible to assign the number of times of repetition of each address to a pattern memory.
CONSTITUTION: In memory unit 1, test pattern information to be sent to tested body 6 is written to block 1a and a pair of repeat information on the number of times of repeatedly sending this information out and a jump instruction for the assignment of a next pattern are also written to block 1b at each address. The test pattern, read out from block 1a is waveform-converted by waveform converter circuit 2 and outputted to tested body 6, and digital comparator 7 makes a comparison to decide on the quality. At the same time, repeat information an jump information read out from block 1b are decoded by detection circuit 3, whose output operates address generating circuit 4 to sent next address assignment information out to unit 1, thereby performong the repetition of the test pattern or the jump.
COPYRIGHT: (C)1980,JPO&Japio
JP9160978A 1978-07-28 1978-07-28 Test pattern generator Pending JPS5518761A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9160978A JPS5518761A (en) 1978-07-28 1978-07-28 Test pattern generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9160978A JPS5518761A (en) 1978-07-28 1978-07-28 Test pattern generator

Publications (1)

Publication Number Publication Date
JPS5518761A true JPS5518761A (en) 1980-02-09

Family

ID=14031305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9160978A Pending JPS5518761A (en) 1978-07-28 1978-07-28 Test pattern generator

Country Status (1)

Country Link
JP (1) JPS5518761A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57128246U (en) * 1981-02-03 1982-08-10

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57128246U (en) * 1981-02-03 1982-08-10

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