JPS55166753A - Test system for checking circuit - Google Patents

Test system for checking circuit

Info

Publication number
JPS55166753A
JPS55166753A JP7580779A JP7580779A JPS55166753A JP S55166753 A JPS55166753 A JP S55166753A JP 7580779 A JP7580779 A JP 7580779A JP 7580779 A JP7580779 A JP 7580779A JP S55166753 A JPS55166753 A JP S55166753A
Authority
JP
Japan
Prior art keywords
logic
checking
illegal data
output
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7580779A
Other languages
Japanese (ja)
Inventor
Noriyuki Ichinohe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP7580779A priority Critical patent/JPS55166753A/en
Publication of JPS55166753A publication Critical patent/JPS55166753A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To check errors of all checking circuits at a time by pushing an illegal data generation switch on a panel, by adding an illegal data assignment bit to each checking circuit and by performing AND of the output of each checking circuit.
CONSTITUTION: With the illegal data generation switch, a signal of logic "1" is input from the panel to Ar, Br...Cr and output signals 215, 315,...415 generate logic "1" through exclusive OR when Ap, Bp,...Cp have odd parity bits or logic "1" through exclusive OR when even parity bits. According to whether the value of output signal 501 output from AND circuit 50 receiving output signals 215W415 from checking circuits 200W400 is logic "1", checking circuits when illegal data ArWCr are inserted are checked.
COPYRIGHT: (C)1980,JPO&Japio
JP7580779A 1979-06-15 1979-06-15 Test system for checking circuit Pending JPS55166753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7580779A JPS55166753A (en) 1979-06-15 1979-06-15 Test system for checking circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7580779A JPS55166753A (en) 1979-06-15 1979-06-15 Test system for checking circuit

Publications (1)

Publication Number Publication Date
JPS55166753A true JPS55166753A (en) 1980-12-26

Family

ID=13586830

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7580779A Pending JPS55166753A (en) 1979-06-15 1979-06-15 Test system for checking circuit

Country Status (1)

Country Link
JP (1) JPS55166753A (en)

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