JPS55163674A - Memory device - Google Patents

Abstract

PURPOSE:To obtain the time-series logic patterns which are continuous in a high speed, by including the shift register into the word selection circuit. CONSTITUTION:The following indications are given to shift register 40 from the control circuit through interface line flux 50: the contents of the register must be shifted; the reading start bit must be inverted to the reading enabling state in the 1-bit logic state, and the contents of register 40 must be reset at the end of reading respectively. One of FF circuits of register 40 is inverted through flux 50 to shift the contents of register 40. Thus the reading words are selected in sequence, and the bit row of the word memorized is read out in time-series to output line flux 30 of memory circuit 10. Accordingly, the reading word can be selected with no address circuit nor decoder needed at the selecting time of the word. And FF circuits 41-4n on register 40 are reset by the indication given to flux 50 from the control circuit. Thus the word selection can be completed.