JPS5515598A - Decoding method and decoder for multi-bit digital signal - Google Patents

Decoding method and decoder for multi-bit digital signal

Info

Publication number
JPS5515598A
JPS5515598A JP8753979A JP8753979A JPS5515598A JP S5515598 A JPS5515598 A JP S5515598A JP 8753979 A JP8753979 A JP 8753979A JP 8753979 A JP8753979 A JP 8753979A JP S5515598 A JPS5515598 A JP S5515598A
Authority
JP
Japan
Prior art keywords
signal
input signal
decoder
partially
logic circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8753979A
Other languages
English (en)
Other versions
JPS5952463B2 (ja
Inventor
Kenichi Miura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of JPS5515598A publication Critical patent/JPS5515598A/ja
Publication of JPS5952463B2 publication Critical patent/JPS5952463B2/ja
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17704—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns
    • H03K19/17708—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form the logic functions being realised by the interconnection of rows and columns using an AND matrix followed by an OR matrix, i.e. programmable logic arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
    • H03M7/001—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits characterised by the elements used
    • H03M7/005—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits characterised by the elements used using semiconductor devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Theoretical Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Executing Machine-Instructions (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
JP54087539A 1978-07-20 1979-07-12 マルチビットディジタル信号の解読方法およびデコ−ダ Expired JPS5952463B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US000000926950 1978-07-20
US05/926,950 US4438427A (en) 1978-07-20 1978-07-20 Decoder and method utilizing partial and redundant decoding

Publications (2)

Publication Number Publication Date
JPS5515598A true JPS5515598A (en) 1980-02-02
JPS5952463B2 JPS5952463B2 (ja) 1984-12-19

Family

ID=25453943

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54087539A Expired JPS5952463B2 (ja) 1978-07-20 1979-07-12 マルチビットディジタル信号の解読方法およびデコ−ダ

Country Status (4)

Country Link
US (1) US4438427A (ja)
EP (1) EP0007754B1 (ja)
JP (1) JPS5952463B2 (ja)
DE (1) DE2964532D1 (ja)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0232796B1 (en) * 1980-11-24 1991-07-03 Texas Instruments Incorporated Pseudo-microprogramming in microprocessor with compressed control rom and with strip layout of busses, alu and registers
US6853644B1 (en) * 1999-12-22 2005-02-08 Intel Corporation Method and apparatus for driving data packets
KR100384886B1 (ko) * 2000-10-10 2003-05-22 주식회사 케이티 니블 반전 부호 활용 방법 및 그 장치

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3936812A (en) * 1974-12-30 1976-02-03 Ibm Corporation Segmented parallel rail paths for input/output signals

Also Published As

Publication number Publication date
DE2964532D1 (en) 1983-02-24
US4438427A (en) 1984-03-20
EP0007754B1 (en) 1983-01-19
JPS5952463B2 (ja) 1984-12-19
EP0007754A1 (en) 1980-02-06

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