JPS55154633A - Comparison circuit - Google Patents

Comparison circuit

Info

Publication number
JPS55154633A
JPS55154633A JP6302879A JP6302879A JPS55154633A JP S55154633 A JPS55154633 A JP S55154633A JP 6302879 A JP6302879 A JP 6302879A JP 6302879 A JP6302879 A JP 6302879A JP S55154633 A JPS55154633 A JP S55154633A
Authority
JP
Japan
Prior art keywords
output
exclusive logical
objective
circuit
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6302879A
Other languages
Japanese (ja)
Other versions
JPS6112576B2 (en
Inventor
Koji Takao
Masatoshi Tachibana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6302879A priority Critical patent/JPS55154633A/en
Publication of JPS55154633A publication Critical patent/JPS55154633A/en
Publication of JPS6112576B2 publication Critical patent/JPS6112576B2/ja
Granted legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To enable to diagnose independently of the number of input bits of compared objective, by taking a pair of exclusive logical sums between the compared instruction signal and the compared objective signal, delivering them, and detecting a fixed fault through the output at the final stage.
CONSTITUTION: With diagnostic state, an external signal 6 is made to "1", and each comparison instruction signal ii (where; i=1...n) and a comparison objective signal 2i are kept the same value, then the output of an exclusive logical sum circuit 31 is at "1", this is delivered to make the output of an exclusive logical sum circuit 32 to "1" and further the output of an exclusive logical sum circuit 33 to "1". Thus, the output of "1" is propagated to the final state, circuit 3n, and all the output of exclusive logical sums are at "1". If any one in the circuit 3j has a fixed failure of "0", the output of the final stage 3n is at "0" to enable the detection of the fixed failure. Thus, diagnosis can be made independently of the number of input bits of comparison objective.
COPYRIGHT: (C)1980,JPO&Japio
JP6302879A 1979-05-22 1979-05-22 Comparison circuit Granted JPS55154633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6302879A JPS55154633A (en) 1979-05-22 1979-05-22 Comparison circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6302879A JPS55154633A (en) 1979-05-22 1979-05-22 Comparison circuit

Publications (2)

Publication Number Publication Date
JPS55154633A true JPS55154633A (en) 1980-12-02
JPS6112576B2 JPS6112576B2 (en) 1986-04-09

Family

ID=13217457

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6302879A Granted JPS55154633A (en) 1979-05-22 1979-05-22 Comparison circuit

Country Status (1)

Country Link
JP (1) JPS55154633A (en)

Also Published As

Publication number Publication date
JPS6112576B2 (en) 1986-04-09

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