JPS55151817A - Clock reproducing circuit - Google Patents
Clock reproducing circuitInfo
- Publication number
- JPS55151817A JPS55151817A JP5965979A JP5965979A JPS55151817A JP S55151817 A JPS55151817 A JP S55151817A JP 5965979 A JP5965979 A JP 5965979A JP 5965979 A JP5965979 A JP 5965979A JP S55151817 A JPS55151817 A JP S55151817A
- Authority
- JP
- Japan
- Prior art keywords
- positive feedback
- output
- level
- control
- filter
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
Abstract
PURPOSE:To perform the clock reproduction with the reduced phase jitter by detecting the level at the output point of the surface wave filter and then giving the control to the positive feedback amount in order to secure the constant output level. CONSTITUTION:The output which was filtered through elastic surface wave filter 1 and then received an integer-fold cycle delay is amplified 2 and then supplied to analog adder 3. For the two inputs of adder 3, the same phase is secured for the output given from input terminal 4 and that from amplifier 27 and then the analog addition is carried out to be then supplied again to filter 1. This loop of one circulation forms the positive feedback loop at the central frequency region and then detects 6 the level at the output point of filter 1 to give the control to the positive feedback amount. Accordingly, the clock reproduction is possible with the reduced phase jitter and even with the zero continuation of the code pulse of the input signal by giving the control to the positive feedback amount in order to secure the constant output level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5965979A JPS55151817A (en) | 1979-05-17 | 1979-05-17 | Clock reproducing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5965979A JPS55151817A (en) | 1979-05-17 | 1979-05-17 | Clock reproducing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS55151817A true JPS55151817A (en) | 1980-11-26 |
Family
ID=13119542
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5965979A Pending JPS55151817A (en) | 1979-05-17 | 1979-05-17 | Clock reproducing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55151817A (en) |
-
1979
- 1979-05-17 JP JP5965979A patent/JPS55151817A/en active Pending
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