JPS55150605A - Variable gain amplifying circuit - Google Patents
Variable gain amplifying circuitInfo
- Publication number
- JPS55150605A JPS55150605A JP5896179A JP5896179A JPS55150605A JP S55150605 A JPS55150605 A JP S55150605A JP 5896179 A JP5896179 A JP 5896179A JP 5896179 A JP5896179 A JP 5896179A JP S55150605 A JPS55150605 A JP S55150605A
- Authority
- JP
- Japan
- Prior art keywords
- resistance
- fet10
- value
- capacity
- gain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G1/00—Details of arrangements for controlling amplification
- H03G1/0005—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal
- H03G1/0035—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements
- H03G1/007—Circuits characterised by the type of controlling devices operated by a controlling current or voltage signal using continuously variable impedance elements using FET type devices
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
PURPOSE:To control the gain in a wide range while keeping the wide-band frequency characteristic, by adding and leading out output signals of noninversion and inversion amplfiers. CONSTITUTION:The minimum gain of transistor TR14 used in a noninversion amplifier becomes a value obtained by dividing the resistance value of resistance 13 by the parallel impedance of the off-impedance of FET10, which is a resistance change element, and resistance 9, and the gain of TR6 of an inversion amplifier becomes a value obtained by dividing the resistance value of resistance 13 by the parallel impedance of resistance 7 and capacity 8. Normally, since the off-resistance of FET10 is 10<6>OMEGA or more and can be ignored in comparison with the resistance value of resistance 9, values of resistances 7 and 9 are made equal to each other, and the value of capacity 8 is made equal to the capacity value between the drain and the source of FET10. Therefore, even if the voltage of input terminal 20 is raised and the resistance value of FET10 is lowered, the capacity between the drain and the source of FET10 is not changed, and a signal output amplitude approximately proportional reversely to resistance change of FET10 is obtained at output terminal 20. Consequently, the gain can be controlled in a wide range while keeping the wide-band frequency characteristic.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5896179A JPS55150605A (en) | 1979-05-11 | 1979-05-11 | Variable gain amplifying circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5896179A JPS55150605A (en) | 1979-05-11 | 1979-05-11 | Variable gain amplifying circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS55150605A true JPS55150605A (en) | 1980-11-22 |
Family
ID=13099430
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5896179A Pending JPS55150605A (en) | 1979-05-11 | 1979-05-11 | Variable gain amplifying circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS55150605A (en) |
-
1979
- 1979-05-11 JP JP5896179A patent/JPS55150605A/en active Pending
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