JPS5513572A - Gate circuit - Google Patents

Gate circuit

Info

Publication number
JPS5513572A
JPS5513572A JP8633578A JP8633578A JPS5513572A JP S5513572 A JPS5513572 A JP S5513572A JP 8633578 A JP8633578 A JP 8633578A JP 8633578 A JP8633578 A JP 8633578A JP S5513572 A JPS5513572 A JP S5513572A
Authority
JP
Japan
Prior art keywords
trq11
gate
base
trq10
trq12
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8633578A
Other languages
Japanese (ja)
Other versions
JPS5944817B2 (en
Inventor
Koichi Tanaka
Kiyoshi Amasawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Faurecia Clarion Electronics Co Ltd
Original Assignee
Clarion Co Ltd
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarion Co Ltd, NEC Corp, Nippon Electric Co Ltd filed Critical Clarion Co Ltd
Priority to JP8633578A priority Critical patent/JPS5944817B2/en
Publication of JPS5513572A publication Critical patent/JPS5513572A/en
Publication of JPS5944817B2 publication Critical patent/JPS5944817B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G3/00—Gain control in amplifiers or frequency changers
    • H03G3/20—Automatic control
    • H03G3/30—Automatic control in amplifiers having semiconductor devices
    • H03G3/34—Muting amplifier when no signal is present or when only weak signals are present, or caused by the presence of noise signals, e.g. squelch systems
    • H03G3/345—Muting during a short period of time when noise pulses are detected, i.e. blanking

Landscapes

  • Electronic Switches (AREA)
  • Noise Elimination (AREA)

Abstract

PURPOSE:To improve a pulse-property noise removal characteristic by setting the holding voltage level of a gate circuit having a limiter function so that signals at a noise removal time may be fixed and the operation range may be wider and the frequency characteristic may be improved. CONSTITUTION:In respect to transistors TrQ11 and Q12 which constitute the limiter circuit of a pulse-property noise removal circuit having input terminal 8 and output terminal 13, the base of TrQ11 is connected to the collector of TrQ10, and the base of TrQ11 is connected to the base of TrQ12, and TrQ12 is driven by constant current I4. Then, the base of TrQ12 is connected to the emitter of TrQ14 out of TrQ6, Q5, Q13, and Q14 which constitute a buffer amplifier; and in case that a noise having a potential higher than the emitter potential of gate TrQ10 during the turning-off state of gate TrQ11 is inputted, the turning-off state of gate TrQ10 is continued by TrQ16 and capacitor C2, thereby extending the dynamic range and the frequency characteristic.
JP8633578A 1978-07-14 1978-07-14 gate circuit Expired JPS5944817B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8633578A JPS5944817B2 (en) 1978-07-14 1978-07-14 gate circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8633578A JPS5944817B2 (en) 1978-07-14 1978-07-14 gate circuit

Publications (2)

Publication Number Publication Date
JPS5513572A true JPS5513572A (en) 1980-01-30
JPS5944817B2 JPS5944817B2 (en) 1984-11-01

Family

ID=13883965

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8633578A Expired JPS5944817B2 (en) 1978-07-14 1978-07-14 gate circuit

Country Status (1)

Country Link
JP (1) JPS5944817B2 (en)

Also Published As

Publication number Publication date
JPS5944817B2 (en) 1984-11-01

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