JPS5526776A - Video signal processing circuit - Google Patents

Video signal processing circuit

Info

Publication number
JPS5526776A
JPS5526776A JP10023078A JP10023078A JPS5526776A JP S5526776 A JPS5526776 A JP S5526776A JP 10023078 A JP10023078 A JP 10023078A JP 10023078 A JP10023078 A JP 10023078A JP S5526776 A JPS5526776 A JP S5526776A
Authority
JP
Japan
Prior art keywords
terminal
differential amplifier
pedestal
output
potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10023078A
Other languages
Japanese (ja)
Inventor
Yasuta Tomuro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10023078A priority Critical patent/JPS5526776A/en
Publication of JPS5526776A publication Critical patent/JPS5526776A/en
Pending legal-status Critical Current

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  • Picture Signal Circuits (AREA)

Abstract

PURPOSE: To vary a pedestal level without sacrificing an input dynamic range by holding a sampled pedestal potential and by controlling the control electrode of the current absorption element of the 1st differential amplifier by the potential.
CONSTITUTION: A video signal inputted to terminal 41 is passed through the 1st differential amplifier composed of transistors Tr1a, Tr1b and Tr1c and then led out to output terminal 46 by way of buffer Tr2. The pedestal part of this output signal is sampled by the 2nd differential amplifier consisting of Trs 6a, 6b and 6c, sampling pulse application terminal 42, and resistances 18 and 20. Its output is supplied to terminal 42 through Tr5 of the switching circuit and sampling buffers Tr3 and Tr4, and capacitor 51 holds the pedestal output. This potential is applied to the base of current absorption Tr1c and fixed bias 31 is also applied to the base of Tr1b. As a result, when the voltage of terminal 43 is varied, the input operation point of the 1st differential amplifier is not shifted to one side and the outout of terminal 46 can be varied without sacrificing the input dynamic range.
COPYRIGHT: (C)1980,JPO&Japio
JP10023078A 1978-08-16 1978-08-16 Video signal processing circuit Pending JPS5526776A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10023078A JPS5526776A (en) 1978-08-16 1978-08-16 Video signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10023078A JPS5526776A (en) 1978-08-16 1978-08-16 Video signal processing circuit

Publications (1)

Publication Number Publication Date
JPS5526776A true JPS5526776A (en) 1980-02-26

Family

ID=14268465

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10023078A Pending JPS5526776A (en) 1978-08-16 1978-08-16 Video signal processing circuit

Country Status (1)

Country Link
JP (1) JPS5526776A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188335A (en) * 1983-04-08 1984-10-25 三菱電機株式会社 Ground-fault detecting circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59188335A (en) * 1983-04-08 1984-10-25 三菱電機株式会社 Ground-fault detecting circuit
JPH031893B2 (en) * 1983-04-08 1991-01-11 Mitsubishi Electric Corp

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