JPS55134411A - Pulse set-type constant-voltage power source - Google Patents

Pulse set-type constant-voltage power source

Info

Publication number
JPS55134411A
JPS55134411A JP3979779A JP3979779A JPS55134411A JP S55134411 A JPS55134411 A JP S55134411A JP 3979779 A JP3979779 A JP 3979779A JP 3979779 A JP3979779 A JP 3979779A JP S55134411 A JPS55134411 A JP S55134411A
Authority
JP
Japan
Prior art keywords
input
output
pulse
pulse signal
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3979779A
Other languages
Japanese (ja)
Inventor
Toshiyuki Tsukada
Susumu Hikichi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP3979779A priority Critical patent/JPS55134411A/en
Publication of JPS55134411A publication Critical patent/JPS55134411A/en
Pending legal-status Critical Current

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  • Control Of Electrical Variables (AREA)

Abstract

PURPOSE: To obtain a set circuit which controls the output voltage throughout a wide range, by controlling the output voltage by an external pulse signal.
CONSTITUTION: The pulse set input is input to UP pulse or DOWN pulse input terminal and is converted to a U/D signal and clock pulses. UP and DOWN input pulses of an FF are connected to the open collector of a contactless transistor, and UP/DOWN input signals become H-level in case of no pulse output. When pulses are input to the UP side and the UP side becomes L-level, the output of the FF becomes H and is held until the pulse signal inputs to the DN side. In case that the pulse signal is input to the DN side, the output of the FF becomes L-level. Meanwhile, when input pulses are input to the UP side and the DN side is H-level, the pulse signal is output to the output of NAND gate A3, and the pulse signal is output similarly when the pulse signal is input to the DN side. That is, only when the pulse signal is input to the UP side or the DN side, the clock signal is output to the UP/DN counter.
COPYRIGHT: (C)1980,JPO&Japio
JP3979779A 1979-04-04 1979-04-04 Pulse set-type constant-voltage power source Pending JPS55134411A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3979779A JPS55134411A (en) 1979-04-04 1979-04-04 Pulse set-type constant-voltage power source

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3979779A JPS55134411A (en) 1979-04-04 1979-04-04 Pulse set-type constant-voltage power source

Publications (1)

Publication Number Publication Date
JPS55134411A true JPS55134411A (en) 1980-10-20

Family

ID=12562936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3979779A Pending JPS55134411A (en) 1979-04-04 1979-04-04 Pulse set-type constant-voltage power source

Country Status (1)

Country Link
JP (1) JPS55134411A (en)

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