JPS5513439A - Protecting system for input/output device - Google Patents

Protecting system for input/output device

Info

Publication number
JPS5513439A
JPS5513439A JP8509978A JP8509978A JPS5513439A JP S5513439 A JPS5513439 A JP S5513439A JP 8509978 A JP8509978 A JP 8509978A JP 8509978 A JP8509978 A JP 8509978A JP S5513439 A JPS5513439 A JP S5513439A
Authority
JP
Japan
Prior art keywords
input
output device
register
key
protecting system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8509978A
Other languages
Japanese (ja)
Other versions
JPS6054692B2 (en
Inventor
Mitsuhiro Amari
Masao Kato
Masanori Kataoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP53085099A priority Critical patent/JPS6054692B2/en
Publication of JPS5513439A publication Critical patent/JPS5513439A/en
Publication of JPS6054692B2 publication Critical patent/JPS6054692B2/en
Expired legal-status Critical Current

Links

Abstract

PURPOSE: To realize both the reading and writing protection for the input/output device with every access bus as well as to decrease the amount of materials for the system.
CONSTITUTION: Identification register 11 is set with 0 or 1 by wake-up given from the channel device to memorize the wake-up system. Command register 12 memorizes the command at that time, and input/output device address register 14 memorizes the address of the input/output device. Selector 19 selects either one of reading protection key 15 and 17 which are shown by register 11 and 14 each. At the same time, selector 20 selects either one of writing protection key 16 and 18 shown by register 11 and 14 each. Key 15 or 17 thus selected is supplied to AND gate 21, and key 16 or 18 selected is supplied to AND gate 22 respectively. The selection can be performed also with the output of decoder 13.
COPYRIGHT: (C)1980,JPO&Japio
JP53085099A 1978-07-14 1978-07-14 I/O device protection method Expired JPS6054692B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53085099A JPS6054692B2 (en) 1978-07-14 1978-07-14 I/O device protection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53085099A JPS6054692B2 (en) 1978-07-14 1978-07-14 I/O device protection method

Publications (2)

Publication Number Publication Date
JPS5513439A true JPS5513439A (en) 1980-01-30
JPS6054692B2 JPS6054692B2 (en) 1985-12-02

Family

ID=13849155

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53085099A Expired JPS6054692B2 (en) 1978-07-14 1978-07-14 I/O device protection method

Country Status (1)

Country Link
JP (1) JPS6054692B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62122196A (en) * 1985-11-21 1987-06-03 日立コンデンサ株式会社 Manufacture of multilayer wiring board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62122196A (en) * 1985-11-21 1987-06-03 日立コンデンサ株式会社 Manufacture of multilayer wiring board

Also Published As

Publication number Publication date
JPS6054692B2 (en) 1985-12-02

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