JPS5621259A - Tracer control system - Google Patents

Tracer control system

Info

Publication number
JPS5621259A
JPS5621259A JP9660079A JP9660079A JPS5621259A JP S5621259 A JPS5621259 A JP S5621259A JP 9660079 A JP9660079 A JP 9660079A JP 9660079 A JP9660079 A JP 9660079A JP S5621259 A JPS5621259 A JP S5621259A
Authority
JP
Japan
Prior art keywords
address
clock
control circuit
stop
tab
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9660079A
Other languages
Japanese (ja)
Inventor
Koji Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9660079A priority Critical patent/JPS5621259A/en
Publication of JPS5621259A publication Critical patent/JPS5621259A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To make unnecessary the stop of system clock, by bypassing the block during stop and renewing the address information, while the clock to the tracer address block is stopped.
CONSTITUTION: In the address control circuit 2, every time the address renewal clock is input, the address information of the tracer address block (TAB)a0Wan is renewed and if the bypassing of the address is designated, the address is bypassed. Further, if the designated event is detected at the comparison circuit 1, the clock enable control circuit 3 stops the clock to a plurality of TABa0Wan including the TAB designated at present by the address control circuit 2. Further, during the clock stop period to TABa0Wan, the TAB for clock stop is bypassed with the address control circuit 2 and the address information is renewed.
COPYRIGHT: (C)1981,JPO&Japio
JP9660079A 1979-07-28 1979-07-28 Tracer control system Pending JPS5621259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9660079A JPS5621259A (en) 1979-07-28 1979-07-28 Tracer control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9660079A JPS5621259A (en) 1979-07-28 1979-07-28 Tracer control system

Publications (1)

Publication Number Publication Date
JPS5621259A true JPS5621259A (en) 1981-02-27

Family

ID=14169361

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9660079A Pending JPS5621259A (en) 1979-07-28 1979-07-28 Tracer control system

Country Status (1)

Country Link
JP (1) JPS5621259A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57182857A (en) * 1981-05-07 1982-11-10 Hitachi Ltd Program trace accumulating and recording system
JPS5892048A (en) * 1981-11-27 1983-06-01 Nec Corp Tracer
JPS5991721U (en) * 1982-12-13 1984-06-21 マルコン電子株式会社 resin exterior capacitor

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57182857A (en) * 1981-05-07 1982-11-10 Hitachi Ltd Program trace accumulating and recording system
JPH0373012B2 (en) * 1981-05-07 1991-11-20 Hitachi Ltd
JPS5892048A (en) * 1981-11-27 1983-06-01 Nec Corp Tracer
JPS6367697B2 (en) * 1981-11-27 1988-12-27 Nippon Electric Co
JPS5991721U (en) * 1982-12-13 1984-06-21 マルコン電子株式会社 resin exterior capacitor
JPS6344976Y2 (en) * 1982-12-13 1988-11-22

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