JPS55127629A - Data processor - Google Patents

Data processor

Info

Publication number
JPS55127629A
JPS55127629A JP3323879A JP3323879A JPS55127629A JP S55127629 A JPS55127629 A JP S55127629A JP 3323879 A JP3323879 A JP 3323879A JP 3323879 A JP3323879 A JP 3323879A JP S55127629 A JPS55127629 A JP S55127629A
Authority
JP
Japan
Prior art keywords
data transfer
instructions
ended
data
queues
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3323879A
Other languages
Japanese (ja)
Inventor
Toshihiro Arima
Mitsukuni Tsuboya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3323879A priority Critical patent/JPS55127629A/en
Publication of JPS55127629A publication Critical patent/JPS55127629A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To improve the processing performance of CPU by adding an instruction by which data transfer has ended to the end of the queue of instructions by which the data transfer has ended.
CONSTITUTION: In a data processor equipped with hardware enabling the queue of commands to be used as an interface, data transfer unit 15 has input-output bus 14, main memory 16 is stored with programs and data, and CPU17 reads sequentially programs in memory 16 to execute instructions. Then, unit 15 takes the initial instructions out from queues 33...35 of commands in queue for data transfer to bring the data transfer to effect, and instructions by which this data transfer has ended are added through logic to the ends of queues 31 and 32 of instructions by which the data transfer has ended. Consequently, equipping the data processor with the hardware enabling the queues of commands to be used as an interface results in the improvement of the processing performance of CPU.
COPYRIGHT: (C)1980,JPO&Japio
JP3323879A 1979-03-23 1979-03-23 Data processor Pending JPS55127629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3323879A JPS55127629A (en) 1979-03-23 1979-03-23 Data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3323879A JPS55127629A (en) 1979-03-23 1979-03-23 Data processor

Publications (1)

Publication Number Publication Date
JPS55127629A true JPS55127629A (en) 1980-10-02

Family

ID=12380876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3323879A Pending JPS55127629A (en) 1979-03-23 1979-03-23 Data processor

Country Status (1)

Country Link
JP (1) JPS55127629A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6371755A (en) * 1986-09-12 1988-04-01 Fujitsu Ltd Method for controlling real time execution

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6371755A (en) * 1986-09-12 1988-04-01 Fujitsu Ltd Method for controlling real time execution

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