JPS55124326A - Phase control circuit - Google Patents

Phase control circuit

Info

Publication number
JPS55124326A
JPS55124326A JP3279379A JP3279379A JPS55124326A JP S55124326 A JPS55124326 A JP S55124326A JP 3279379 A JP3279379 A JP 3279379A JP 3279379 A JP3279379 A JP 3279379A JP S55124326 A JPS55124326 A JP S55124326A
Authority
JP
Japan
Prior art keywords
source
resistance
drain
circuit
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3279379A
Other languages
Japanese (ja)
Inventor
Shigeru Arita
Taku Kawahara
Minoru Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP3279379A priority Critical patent/JPS55124326A/en
Publication of JPS55124326A publication Critical patent/JPS55124326A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
    • H03K2005/0015—Layout of the delay element
    • H03K2005/00195—Layout of the delay element using FET's

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Pulse Circuits (AREA)

Abstract

PURPOSE:To reduce the variation of the resistance value and then securing the correct control for the phase difference between the reference pulse and the phase inverse pulse by utilizing the resistance between the drain and the source of the MOSFET for the resistance which is used for the CR delay circuit for phase control, thus eliminating the malfunction of the circuit. CONSTITUTION:The MOS inverter is formed with N-type MOSFET2 and P-type MOSFET1 of 1st circuit part A which gives the process to the reference pulse. And the drain is connected to the source of P-type MOSFET17 between the source of FET1 and drain power terminal 15; and furthermore the drain-source of N-type MOSFET18 is connected between the source of FET2 and source power terminal 16. And the resistance between the drains and the sources of FETS17 and 18 is utilized for the resistance forming the delay circuit. Then the correct control is given to the phase difference to 180 deg. against the phase inverse pulse which is processed via the MOS inverter at 2nd circuit part B where the process is given to the phase inverse pulse. Accordingly, the malfunction caused by the circuit can be eliminated.
JP3279379A 1979-03-19 1979-03-19 Phase control circuit Pending JPS55124326A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3279379A JPS55124326A (en) 1979-03-19 1979-03-19 Phase control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3279379A JPS55124326A (en) 1979-03-19 1979-03-19 Phase control circuit

Publications (1)

Publication Number Publication Date
JPS55124326A true JPS55124326A (en) 1980-09-25

Family

ID=12368723

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3279379A Pending JPS55124326A (en) 1979-03-19 1979-03-19 Phase control circuit

Country Status (1)

Country Link
JP (1) JPS55124326A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141120A (en) * 1981-02-26 1982-09-01 Nec Corp Driving method for ccd comb type filter
JPS5966218A (en) * 1982-10-08 1984-04-14 Hitachi Micro Comput Eng Ltd Delay circuit
EP0176226A2 (en) * 1984-08-23 1986-04-02 Fujitsu Limited Semiconductor circuit
JPH01212020A (en) * 1988-02-18 1989-08-25 Nec Ic Microcomput Syst Ltd Delay circuit

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53106532A (en) * 1977-02-28 1978-09-16 Toshiba Corp Logic circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53106532A (en) * 1977-02-28 1978-09-16 Toshiba Corp Logic circuit

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141120A (en) * 1981-02-26 1982-09-01 Nec Corp Driving method for ccd comb type filter
JPH0128534B2 (en) * 1981-02-26 1989-06-02 Nippon Electric Co
JPS5966218A (en) * 1982-10-08 1984-04-14 Hitachi Micro Comput Eng Ltd Delay circuit
EP0176226A2 (en) * 1984-08-23 1986-04-02 Fujitsu Limited Semiconductor circuit
JPH01212020A (en) * 1988-02-18 1989-08-25 Nec Ic Microcomput Syst Ltd Delay circuit

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