JPS55121665A - Method of fabricating semiconductor device - Google Patents

Method of fabricating semiconductor device

Info

Publication number
JPS55121665A
JPS55121665A JP2967579A JP2967579A JPS55121665A JP S55121665 A JPS55121665 A JP S55121665A JP 2967579 A JP2967579 A JP 2967579A JP 2967579 A JP2967579 A JP 2967579A JP S55121665 A JPS55121665 A JP S55121665A
Authority
JP
Japan
Prior art keywords
film
substrate
oxide film
ion
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2967579A
Other languages
Japanese (ja)
Inventor
Kazuaki Miyata
Yoji Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2967579A priority Critical patent/JPS55121665A/en
Publication of JPS55121665A publication Critical patent/JPS55121665A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To readily and accurately form an infinitesimal impurity diffused layer in a semiconductor device by throttling an implanted ion beam by utilizing the step difference between a semiconductor substrate and a mask layer formed on the surface of the substrate to implant the ion thereto. CONSTITUTION:An oxide film 2, a nitride film 3 and a photoresist film 4 are sequentially formed on a p-type silicon substrate 1 to partition between an active region 5 and a passivation region 6 thereon. Then, a photoresist film 14 is formed thereon, ion is implanted to the width narrower than that of an opening 13 by utilizing a mask at the end of the step from the surface of the substrate 1 of the film 14. Then, the films 14, 4 are removed, a field oxide film 8 is thermally grown, and the nitride film 3 is removed. Then, a gate oxide film 9, a polysilicon gate electrode 10 and an n-type source region 11, n-type drain region 12 are formed to complete a MOSFET.
JP2967579A 1979-03-13 1979-03-13 Method of fabricating semiconductor device Pending JPS55121665A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2967579A JPS55121665A (en) 1979-03-13 1979-03-13 Method of fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2967579A JPS55121665A (en) 1979-03-13 1979-03-13 Method of fabricating semiconductor device

Publications (1)

Publication Number Publication Date
JPS55121665A true JPS55121665A (en) 1980-09-18

Family

ID=12282679

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2967579A Pending JPS55121665A (en) 1979-03-13 1979-03-13 Method of fabricating semiconductor device

Country Status (1)

Country Link
JP (1) JPS55121665A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5004701A (en) * 1988-01-29 1991-04-02 Nec Corporation Method of forming isolation region in integrated circuit semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5004701A (en) * 1988-01-29 1991-04-02 Nec Corporation Method of forming isolation region in integrated circuit semiconductor device

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