JPS55118628A - Manufacturing method of epitaxial wafer - Google Patents

Manufacturing method of epitaxial wafer

Info

Publication number
JPS55118628A
JPS55118628A JP2530179A JP2530179A JPS55118628A JP S55118628 A JPS55118628 A JP S55118628A JP 2530179 A JP2530179 A JP 2530179A JP 2530179 A JP2530179 A JP 2530179A JP S55118628 A JPS55118628 A JP S55118628A
Authority
JP
Japan
Prior art keywords
vapor phase
phase deposition
flow rate
carrier gas
lower value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2530179A
Other languages
Japanese (ja)
Inventor
Masahiro Kamiya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2530179A priority Critical patent/JPS55118628A/en
Publication of JPS55118628A publication Critical patent/JPS55118628A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

PURPOSE:To improve uniformity of etched quantity within a batch by a method wherein the flow rate of carrier gas is set at a lower value than that of vapor phase deposition when vapor phase etching is performed. CONSTITUTION:The flow rate of carrier gas is depressed to a lower value than that of vapor phase deposition process, and vapor phase etching is performed. For example when epitaxial growth is performed utilizing SiH4 as a silicon source, the flow rate of a carrier gas (H2) during vapor phase deposition is increased to supress ununiformity of epitaxial film thickness due to lower temperature for thermal decomposition of SiH4 than that for vapor phase deposition. And when vapor phase etching utilizing HCl is performed to clean the substrate before vapor phase deposition process, flowing of raw HCl gas along the gas flow direction to a outlet side is hindered by depressing carrier gas flow rate to a lower value than that of vapor phase deposition. By that method uniformity of the etched quantity within a batch is improved without too much etched quantity at the outlet side.
JP2530179A 1979-03-05 1979-03-05 Manufacturing method of epitaxial wafer Pending JPS55118628A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2530179A JPS55118628A (en) 1979-03-05 1979-03-05 Manufacturing method of epitaxial wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2530179A JPS55118628A (en) 1979-03-05 1979-03-05 Manufacturing method of epitaxial wafer

Publications (1)

Publication Number Publication Date
JPS55118628A true JPS55118628A (en) 1980-09-11

Family

ID=12162185

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2530179A Pending JPS55118628A (en) 1979-03-05 1979-03-05 Manufacturing method of epitaxial wafer

Country Status (1)

Country Link
JP (1) JPS55118628A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180035500A1 (en) * 2016-07-28 2018-02-01 Lumileds Llc Dimming led circuit augmenting dc/dc controller integrated circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180035500A1 (en) * 2016-07-28 2018-02-01 Lumileds Llc Dimming led circuit augmenting dc/dc controller integrated circuit
US10959306B2 (en) 2016-07-28 2021-03-23 Lumileds Llc Dimming LED circuit augmenting DC/DC controller integrated circuit

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