JPS55118274A - Vertical deflection circuit - Google Patents

Vertical deflection circuit

Info

Publication number
JPS55118274A
JPS55118274A JP2586679A JP2586679A JPS55118274A JP S55118274 A JPS55118274 A JP S55118274A JP 2586679 A JP2586679 A JP 2586679A JP 2586679 A JP2586679 A JP 2586679A JP S55118274 A JPS55118274 A JP S55118274A
Authority
JP
Japan
Prior art keywords
voltage
power supply
deflection
terminal
supply voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2586679A
Other languages
Japanese (ja)
Inventor
Katsuhiro Takagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2586679A priority Critical patent/JPS55118274A/en
Publication of JPS55118274A publication Critical patent/JPS55118274A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K4/00—Generating pulses having essentially a finite slope or stepped portions
    • H03K4/06—Generating pulses having essentially a finite slope or stepped portions having triangular shape
    • H03K4/08—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape
    • H03K4/48—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices
    • H03K4/60—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth current is produced through an inductor
    • H03K4/69—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth current is produced through an inductor using a semiconductor device operating as an amplifier
    • H03K4/696—Generating pulses having essentially a finite slope or stepped portions having triangular shape having sawtooth shape using as active elements semiconductor devices in which a sawtooth current is produced through an inductor using a semiconductor device operating as an amplifier using means for reducing power dissipation or for shortening the flyback time, e.g. applying a higher voltage during flyback time

Landscapes

  • Details Of Television Scanning (AREA)

Abstract

PURPOSE:To reduce the power consumption, by operating the vertical deflection output circuit at higher power supply voltage on blanking pulse period and operating it at lower power supply voltage determined with the voltage dynamic of output for the deflection period and increasing the power supply voltage utilization factor. CONSTITUTION:The vertical deflection signal in saw tooth wave in response to the vertical scanning and vertical blanking period is amplified at the preamplifier 1, this output drives the output transistors Trs7, 8 and Trs9, 10, deflection current is fed to the deflection yoke 13, and the flyback pulse produced in this yoke 13 is clamped at the clamp diode 11. The voltage +B1 from the high voltage terminal 21 is fed to the first power supply voltage applied terminal of the amplifier 1, and the low voltage side voltage +B2 from the power supply terminal 22 is fed to the power supply terminal of Trs7, 8 via the diode 20. Further, the resistor 18 is connected between the terminals 21 and 22, the capacitor 19 is connected to the terminal 22, Trs7, 8 are cut off at the deflection period, the capacitor 19 is charged up at the voltage +B1 with lower operation voltage to increase the utilization factor of power supply voltage.
JP2586679A 1979-03-06 1979-03-06 Vertical deflection circuit Pending JPS55118274A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2586679A JPS55118274A (en) 1979-03-06 1979-03-06 Vertical deflection circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2586679A JPS55118274A (en) 1979-03-06 1979-03-06 Vertical deflection circuit

Publications (1)

Publication Number Publication Date
JPS55118274A true JPS55118274A (en) 1980-09-11

Family

ID=12177712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2586679A Pending JPS55118274A (en) 1979-03-06 1979-03-06 Vertical deflection circuit

Country Status (1)

Country Link
JP (1) JPS55118274A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5982115A (en) * 1990-03-28 1999-11-09 Deutsche Thomson Brandt Gmbh Circuit arrangement for producing a vertical frequency deflection current

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5099217A (en) * 1973-12-28 1975-08-06

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5099217A (en) * 1973-12-28 1975-08-06

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5982115A (en) * 1990-03-28 1999-11-09 Deutsche Thomson Brandt Gmbh Circuit arrangement for producing a vertical frequency deflection current

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