JPS55115760A - Phase synchronism circuit - Google Patents

Phase synchronism circuit

Info

Publication number
JPS55115760A
JPS55115760A JP2311479A JP2311479A JPS55115760A JP S55115760 A JPS55115760 A JP S55115760A JP 2311479 A JP2311479 A JP 2311479A JP 2311479 A JP2311479 A JP 2311479A JP S55115760 A JPS55115760 A JP S55115760A
Authority
JP
Japan
Prior art keywords
phase
signal
input
circuit
input signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2311479A
Other languages
Japanese (ja)
Inventor
Tatsuki Hayashi
Akira Kawasaki
Toshiyuki Yamamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2311479A priority Critical patent/JPS55115760A/en
Publication of JPS55115760A publication Critical patent/JPS55115760A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop

Abstract

PURPOSE:To obtain phase synchronism to intermittent input signal, by detecting the presence of the input signal in a given time and obtaining input phase comparison signal through the selection of the input signal and the oscillation circuit output signal with this detection signal. CONSTITUTION:When the input signal 1 is present, this signal 1 is fed from the selection circuit 14 to the phase detector 3, and phase control is made with the phase synchronizing loop consisting of the low pass filter 4, VCO5 and frequency dividing circuit 6. If the input signal 1 is absent, the signal 16 in which the reference signal 2 is in phase inverted with the phase inversion circuit 15 is fed to the phase detector 3 via the selection circuit 14. The phase detector 3 controls the phase synchronizing loop by detecting the phase difference at the leading point of the input phase comparison signal 11 and of the output reference signal 2. Thus, the carrier output less in phase variation can be obtained.
JP2311479A 1979-02-28 1979-02-28 Phase synchronism circuit Pending JPS55115760A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2311479A JPS55115760A (en) 1979-02-28 1979-02-28 Phase synchronism circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2311479A JPS55115760A (en) 1979-02-28 1979-02-28 Phase synchronism circuit

Publications (1)

Publication Number Publication Date
JPS55115760A true JPS55115760A (en) 1980-09-05

Family

ID=12101449

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2311479A Pending JPS55115760A (en) 1979-02-28 1979-02-28 Phase synchronism circuit

Country Status (1)

Country Link
JP (1) JPS55115760A (en)

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