JPS55115752A - Synchronizing system for digital radio communication - Google Patents

Synchronizing system for digital radio communication

Info

Publication number
JPS55115752A
JPS55115752A JP2267179A JP2267179A JPS55115752A JP S55115752 A JPS55115752 A JP S55115752A JP 2267179 A JP2267179 A JP 2267179A JP 2267179 A JP2267179 A JP 2267179A JP S55115752 A JPS55115752 A JP S55115752A
Authority
JP
Japan
Prior art keywords
output
phase
oscillator
signal
synchronizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2267179A
Other languages
Japanese (ja)
Inventor
Toru Omori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2267179A priority Critical patent/JPS55115752A/en
Publication of JPS55115752A publication Critical patent/JPS55115752A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To enable self-running with the frequency stored up to now, by providing the phase synchronizing oscillator operated in following to the input synchronizing signal with the digital carrier multiplex unit and detecting the missing of input synchronizing signal or phase shift. CONSTITUTION:The phase detector 9 detects the phase difference between the input synchronizing signal and the output signal of the voltage controlled type crystal oscillator 14 being the output of the phase synchronizing oscillator 8. The detection output is given to the rate amplifier 10 and the integrator 11 with branching, it is added with the adder 12 and converted into the output signal averaged in timing. This signal is returned to the control input of the oscillator 14 via the selector 13. The output of the adder 12 is inputted also to the memory unit 15 and the output is inputted to the selector 13. The output of the oscillator 14 is phase synchronized to the input synchronizing signal with the phase synchronizing loop in the response speed determined with the time constant of the rate amplifier 10 and the integrator 11 at all times.
JP2267179A 1979-02-27 1979-02-27 Synchronizing system for digital radio communication Pending JPS55115752A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2267179A JPS55115752A (en) 1979-02-27 1979-02-27 Synchronizing system for digital radio communication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2267179A JPS55115752A (en) 1979-02-27 1979-02-27 Synchronizing system for digital radio communication

Publications (1)

Publication Number Publication Date
JPS55115752A true JPS55115752A (en) 1980-09-05

Family

ID=12089305

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2267179A Pending JPS55115752A (en) 1979-02-27 1979-02-27 Synchronizing system for digital radio communication

Country Status (1)

Country Link
JP (1) JPS55115752A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60194850A (en) * 1984-03-16 1985-10-03 Fujitsu Ltd Phase locked loop transmitter-receiver

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60194850A (en) * 1984-03-16 1985-10-03 Fujitsu Ltd Phase locked loop transmitter-receiver

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