JPS55112663A - File control unit - Google Patents

File control unit

Info

Publication number
JPS55112663A
JPS55112663A JP1967379A JP1967379A JPS55112663A JP S55112663 A JPS55112663 A JP S55112663A JP 1967379 A JP1967379 A JP 1967379A JP 1967379 A JP1967379 A JP 1967379A JP S55112663 A JPS55112663 A JP S55112663A
Authority
JP
Japan
Prior art keywords
unit
sector address
lowering
processor
memories
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1967379A
Other languages
Japanese (ja)
Inventor
Kunio Nakamura
Hiroshi Kuwabara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1967379A priority Critical patent/JPS55112663A/en
Publication of JPS55112663A publication Critical patent/JPS55112663A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To avoid in lowering the entire throughput for the system, by coincident detection between the sector address on the rotary memory unit designated from the processor with the sector address read out from the rotary memory unit.
CONSTITUTION: In the data transfer between the processor 100 and the rotary magnetic memory unit 200 having the sector format of the fixed length, the sector address on the unit 200 designated from the processor 100 and the sector address read out from the unit 200 are compared for coincidence detection. Further, after designating the data write-in or readout to the buffer memories 5 and 6 and the confirmation of all the data accessed on the memories 5 and 6, if address coincidence detection is present, the data transfer is controlled between the units 100 and 200 via the memories 5 and 6 in response to the access mode designation output. Thus, if data transfer is disable due to lowering in the data processing ability of the unit 100, the lowering in the throughput of the entire system can be avoided.
COPYRIGHT: (C)1980,JPO&Japio
JP1967379A 1979-02-23 1979-02-23 File control unit Pending JPS55112663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1967379A JPS55112663A (en) 1979-02-23 1979-02-23 File control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1967379A JPS55112663A (en) 1979-02-23 1979-02-23 File control unit

Publications (1)

Publication Number Publication Date
JPS55112663A true JPS55112663A (en) 1980-08-30

Family

ID=12005749

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1967379A Pending JPS55112663A (en) 1979-02-23 1979-02-23 File control unit

Country Status (1)

Country Link
JP (1) JPS55112663A (en)

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