JPS55112053A - Analog input circuit - Google Patents

Analog input circuit

Info

Publication number
JPS55112053A
JPS55112053A JP1999279A JP1999279A JPS55112053A JP S55112053 A JPS55112053 A JP S55112053A JP 1999279 A JP1999279 A JP 1999279A JP 1999279 A JP1999279 A JP 1999279A JP S55112053 A JPS55112053 A JP S55112053A
Authority
JP
Japan
Prior art keywords
circuits
analog input
zero
power
cpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1999279A
Other languages
Japanese (ja)
Inventor
Hiroshi Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1999279A priority Critical patent/JPS55112053A/en
Publication of JPS55112053A publication Critical patent/JPS55112053A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
    • H04B14/04—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation using pulse code modulation
    • H04B14/044—Sample and hold circuits

Abstract

PURPOSE:To eliminate the noise caused by the power source by giving the sample holding to the input signal corresponding to the area near the zero cross of the power AC voltage. CONSTITUTION:The analog input to analog input terminals I1-In are held at holding circuits H1-Hn via switching circuits S1-Sn. The output of the holding circuits undergo the A/D conversion in sequence via the multiplexer circuit controlled by the CPU to be supplied to the CPU. Circuits S1-Sn are opened by circuit Z which detects the zero-cross point of the power voltage supplied from power terminal E and for the time close to the zero-cross point. And the input signals for that time are held at circuits H1-Hn.
JP1999279A 1979-02-22 1979-02-22 Analog input circuit Pending JPS55112053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1999279A JPS55112053A (en) 1979-02-22 1979-02-22 Analog input circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1999279A JPS55112053A (en) 1979-02-22 1979-02-22 Analog input circuit

Publications (1)

Publication Number Publication Date
JPS55112053A true JPS55112053A (en) 1980-08-29

Family

ID=12014654

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1999279A Pending JPS55112053A (en) 1979-02-22 1979-02-22 Analog input circuit

Country Status (1)

Country Link
JP (1) JPS55112053A (en)

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