JPS55111146A - Semiconductor integrated circuit - Google Patents

Semiconductor integrated circuit

Info

Publication number
JPS55111146A
JPS55111146A JP1937179A JP1937179A JPS55111146A JP S55111146 A JPS55111146 A JP S55111146A JP 1937179 A JP1937179 A JP 1937179A JP 1937179 A JP1937179 A JP 1937179A JP S55111146 A JPS55111146 A JP S55111146A
Authority
JP
Japan
Prior art keywords
region
type
insulating film
integrated circuit
islet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1937179A
Other languages
Japanese (ja)
Inventor
Takashi Narukawa
Shinichi Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
NEC Engineering Ltd
Original Assignee
NEC Corp
NEC Engineering Ltd
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, NEC Engineering Ltd, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1937179A priority Critical patent/JPS55111146A/en
Publication of JPS55111146A publication Critical patent/JPS55111146A/en
Pending legal-status Critical Current

Links

Landscapes

  • Element Separation (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Bipolar Integrated Circuits (AREA)

Abstract

PURPOSE: To make reliability higher by protecting integrated circuit against abnormal voltage by a construction wherein above the islet region between the isolation junction region and high density region that lies in the islet region the metal layer which has certain voltage level is disposed through an insulating film.
CONSTITUTION: An n-type silicon epitaxial layer 16 is formed on the p-type silicon substrate 17 and islet region is divided by the p-type isolation region 18. In the inlet region the p-type base region 20, n-type emitter region 19 and collector region 13 of high impurity density are formed and they are covered by the insulating film 15. The insulating film 15 which covers the epitaxial layer between the n+-type high density area 13 and the isolation area 18 has proper thickness and on it there is a gate structure covered with the metal wiring 12. By this construction when abnormal voltage is applied through the metal wiring 14 an p-type reversed area is generated under the metal wiring 12 and breakdown takes place at lower voltage and absorption of abnormal voltage is performed and thus protection of integrated circuit is possible.
COPYRIGHT: (C)1980,JPO&Japio
JP1937179A 1979-02-21 1979-02-21 Semiconductor integrated circuit Pending JPS55111146A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1937179A JPS55111146A (en) 1979-02-21 1979-02-21 Semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1937179A JPS55111146A (en) 1979-02-21 1979-02-21 Semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS55111146A true JPS55111146A (en) 1980-08-27

Family

ID=11997468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1937179A Pending JPS55111146A (en) 1979-02-21 1979-02-21 Semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS55111146A (en)

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