JPS5510691A - Data supervisory system - Google Patents

Data supervisory system

Info

Publication number
JPS5510691A
JPS5510691A JP8430478A JP8430478A JPS5510691A JP S5510691 A JPS5510691 A JP S5510691A JP 8430478 A JP8430478 A JP 8430478A JP 8430478 A JP8430478 A JP 8430478A JP S5510691 A JPS5510691 A JP S5510691A
Authority
JP
Japan
Prior art keywords
data
error
circuit
parity check
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8430478A
Other languages
Japanese (ja)
Other versions
JPS584364B2 (en
Inventor
Taiho Higuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53084304A priority Critical patent/JPS584364B2/en
Publication of JPS5510691A publication Critical patent/JPS5510691A/en
Publication of JPS584364B2 publication Critical patent/JPS584364B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Detection And Prevention Of Errors In Transmission (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)

Abstract

PURPOSE: To improve reliability by detecting an error in a data transmitter by carrying on a parity check from the generation of a data effective strobe signal until the arrival of a data reception confirmation signal in a data superviosry system.
CONSTITUTION: A parity check circuit is indicated by 6, and NAND circuits are by 7, 8, 12 and 13. Circuit 6 outputs "0" when the check result is normal and "1" when an error occurs. Once the output of circuit 12 becomes "1" making an error display signal "1", the error display state is held even after the output of circuit 7 returns to "1". Then, the error display is reset by error reset signal 5 generated at an adequate point in time. In this case, since the data supervisory circuit is free from the clock timing conditions, the period when an error check is made is T and the parity check is carried on until transmitted data are received by a party unit.
COPYRIGHT: (C)1980,JPO&Japio
JP53084304A 1978-07-11 1978-07-11 Data monitoring method Expired JPS584364B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53084304A JPS584364B2 (en) 1978-07-11 1978-07-11 Data monitoring method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53084304A JPS584364B2 (en) 1978-07-11 1978-07-11 Data monitoring method

Publications (2)

Publication Number Publication Date
JPS5510691A true JPS5510691A (en) 1980-01-25
JPS584364B2 JPS584364B2 (en) 1983-01-26

Family

ID=13826736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53084304A Expired JPS584364B2 (en) 1978-07-11 1978-07-11 Data monitoring method

Country Status (1)

Country Link
JP (1) JPS584364B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51112215A (en) * 1975-03-28 1976-10-04 Hitachi Ltd Error control system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51112215A (en) * 1975-03-28 1976-10-04 Hitachi Ltd Error control system

Also Published As

Publication number Publication date
JPS584364B2 (en) 1983-01-26

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