JPS55105343A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device

Info

Publication number
JPS55105343A
JPS55105343A JP1260979A JP1260979A JPS55105343A JP S55105343 A JPS55105343 A JP S55105343A JP 1260979 A JP1260979 A JP 1260979A JP 1260979 A JP1260979 A JP 1260979A JP S55105343 A JPS55105343 A JP S55105343A
Authority
JP
Japan
Prior art keywords
region
diffused
regions
layer
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1260979A
Other languages
Japanese (ja)
Inventor
Satoshi Arai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Instruments Inc
Original Assignee
Seiko Instruments Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Instruments Inc filed Critical Seiko Instruments Inc
Priority to JP1260979A priority Critical patent/JPS55105343A/en
Publication of JPS55105343A publication Critical patent/JPS55105343A/en
Pending legal-status Critical Current

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  • Element Separation (AREA)

Abstract

PURPOSE: To simplify manufacturing process; in forming a plurality of semiconductor elements on the same substrate, and in providing the grooves for separation and for taking out electrodes; by forming them by using anisotropic etching in the same process.
CONSTITUTION: A plurality of N+-embeded regions 13 are diffused and formed on a P-type semiconductor substrate 10, and an N---layer 16 is epitaxially grown on all over the surface. Then, a V-shaped concave groove 11 for separating a layer 16 including the regions 13 and an electrode-taking-out groove 12 which pierces throug the region 13 in the island region are formed so as to reach the substrate 10 by anisotropic etching. At this time, the formations mentioned above are performed by one process. Thereafter, a P-type base region 15 is diffused and formed in the island region by an ordinary method, an N-type emitter region 14 is provided in said region 15, an N-type isolated layer 23 is diffused and formed on the side walls and the bottom of the groove 12, and all the surface is protected by an oxide film 17. Windows are opened through said film, and electrodes are attached to the respective regions.
COPYRIGHT: (C)1980,JPO&Japio
JP1260979A 1979-02-06 1979-02-06 Manufacturing method of semiconductor device Pending JPS55105343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1260979A JPS55105343A (en) 1979-02-06 1979-02-06 Manufacturing method of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1260979A JPS55105343A (en) 1979-02-06 1979-02-06 Manufacturing method of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55105343A true JPS55105343A (en) 1980-08-12

Family

ID=11810096

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1260979A Pending JPS55105343A (en) 1979-02-06 1979-02-06 Manufacturing method of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55105343A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06310591A (en) * 1993-04-23 1994-11-04 Matsushita Electric Works Ltd Semiconductor device and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06310591A (en) * 1993-04-23 1994-11-04 Matsushita Electric Works Ltd Semiconductor device and manufacture thereof

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