JPS55103077A - Power converter - Google Patents

Power converter

Info

Publication number
JPS55103077A
JPS55103077A JP873279A JP873279A JPS55103077A JP S55103077 A JPS55103077 A JP S55103077A JP 873279 A JP873279 A JP 873279A JP 873279 A JP873279 A JP 873279A JP S55103077 A JPS55103077 A JP S55103077A
Authority
JP
Japan
Prior art keywords
output
set value
inverter units
timer circuit
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP873279A
Other languages
Japanese (ja)
Inventor
Ikuo Yasuoka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP873279A priority Critical patent/JPS55103077A/en
Publication of JPS55103077A publication Critical patent/JPS55103077A/en
Pending legal-status Critical Current

Links

Landscapes

  • Inverter Devices (AREA)
  • Filters And Equalizers (AREA)
  • Electric Propulsion And Braking For Vehicles (AREA)
  • Power Conversion In General (AREA)

Abstract

PURPOSE: To quickly perform commutation fault protection at the time of line disconnection, by controlling the semiconductor switching elements of inverter units by the output of a level comparison circuit which compares the voltage of a filter capacitor with a set value.
CONSTITUTION: The output 9a of a DC transformer 9 for detecting the terminal voltage of the filter capacitor 3 of a filter circuit F is compared with a first voltage set value VO by a level comparison output unit 11. When the output 9a falls below the set value VO due to line disconnection or the like, another output 11a is produced and supplied to a timer circuit 12. A gate stop signal is applied to three-phase inverter units 4, 5 by the output 12a of the timer circuit 12. When the output 9a increases above a second set value V1(V1>VO), a gate signal is delayed by a time TO by the off-delay timer circuit 12 and applied to the semiconductor control elements of the three-phase inverter units 4, 5 to properly operate these inverter units.
COPYRIGHT: (C)1980,JPO&Japio
JP873279A 1979-01-30 1979-01-30 Power converter Pending JPS55103077A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP873279A JPS55103077A (en) 1979-01-30 1979-01-30 Power converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP873279A JPS55103077A (en) 1979-01-30 1979-01-30 Power converter

Publications (1)

Publication Number Publication Date
JPS55103077A true JPS55103077A (en) 1980-08-06

Family

ID=11701119

Family Applications (1)

Application Number Title Priority Date Filing Date
JP873279A Pending JPS55103077A (en) 1979-01-30 1979-01-30 Power converter

Country Status (1)

Country Link
JP (1) JPS55103077A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4799697B2 (en) * 2009-10-09 2011-10-26 日本省力機械株式会社 Copying device
JP2016119729A (en) * 2014-12-18 2016-06-30 三菱電機株式会社 Power converter

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4799697B2 (en) * 2009-10-09 2011-10-26 日本省力機械株式会社 Copying device
JP2016119729A (en) * 2014-12-18 2016-06-30 三菱電機株式会社 Power converter

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