JPS5498541A - Code conversion circuit - Google Patents

Code conversion circuit

Info

Publication number
JPS5498541A
JPS5498541A JP594678A JP594678A JPS5498541A JP S5498541 A JPS5498541 A JP S5498541A JP 594678 A JP594678 A JP 594678A JP 594678 A JP594678 A JP 594678A JP S5498541 A JPS5498541 A JP S5498541A
Authority
JP
Japan
Prior art keywords
code conversion
read
given
memory
conversion circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP594678A
Other languages
Japanese (ja)
Other versions
JPS5936780B2 (en
Inventor
Kimimoto Mizuno
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP594678A priority Critical patent/JPS5936780B2/en
Publication of JPS5498541A publication Critical patent/JPS5498541A/en
Publication of JPS5936780B2 publication Critical patent/JPS5936780B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Sewing Machines And Sewing (AREA)
  • Dc Digital Transmission (AREA)

Abstract

PURPOSE: To increase the conversion speed, by performing the combination of code conversions of a given number through the utilization of the read only memory and simplifying the constitution of the code conversion circuit, in the tape code conversion circuit used for the control such as automatic embroidery units.
CONSTITUTION: The circuit is provided with the read only memory 16 of a given bits, a pair of reversible counters 17 of a given bit, NAND gates 19 of a given input and two input NAND gate 18. The logic value from tape is inputted to the read only memory 16 of the circuit, the operation by the combination of the outputs is made, and it is fetched with the timing signal CPZ1 to the reversible counter 17. Further, the signal of +1 or -1 is fed to the reversible counter with the timing signal CPZ2 through the NAND gate 19 and the output of code conversion is obtained at the output of the counter 17.
COPYRIGHT: (C)1979,JPO&Japio
JP594678A 1978-01-23 1978-01-23 code conversion circuit Expired JPS5936780B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP594678A JPS5936780B2 (en) 1978-01-23 1978-01-23 code conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP594678A JPS5936780B2 (en) 1978-01-23 1978-01-23 code conversion circuit

Publications (2)

Publication Number Publication Date
JPS5498541A true JPS5498541A (en) 1979-08-03
JPS5936780B2 JPS5936780B2 (en) 1984-09-05

Family

ID=11625053

Family Applications (1)

Application Number Title Priority Date Filing Date
JP594678A Expired JPS5936780B2 (en) 1978-01-23 1978-01-23 code conversion circuit

Country Status (1)

Country Link
JP (1) JPS5936780B2 (en)

Also Published As

Publication number Publication date
JPS5936780B2 (en) 1984-09-05

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