JPS54121020A - Decoder circuit - Google Patents

Decoder circuit

Info

Publication number
JPS54121020A
JPS54121020A JP2969278A JP2969278A JPS54121020A JP S54121020 A JPS54121020 A JP S54121020A JP 2969278 A JP2969278 A JP 2969278A JP 2969278 A JP2969278 A JP 2969278A JP S54121020 A JPS54121020 A JP S54121020A
Authority
JP
Japan
Prior art keywords
length
run
signal
picture signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2969278A
Other languages
Japanese (ja)
Inventor
Masamichi Kawakami
Noriyoshi Ogata
Hiroyuki Hayazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2969278A priority Critical patent/JPS54121020A/en
Publication of JPS54121020A publication Critical patent/JPS54121020A/en
Pending legal-status Critical Current

Links

Landscapes

  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)

Abstract

PURPOSE: To provide the decoding memory with every same bit number of the binary code signal to be decoded and then to utilize the parallel output obtained by introducing the code signal to the shift register in division into the upper and lower rank digits each.
CONSTITUTION: The picture signal of the black run-length is decoded after the picture signal of the white run-length. With arrival of black run-length 10 from input terminal 2, high-speed clock pulse ϕ2 counts up counter 6 via AND gate 5 and is also applied to parallel conversion shift register 13 via OR gate 9 since FF4 is set. As ϕ2 features an extremely high speed, its contents are all set to "1" within the first half bit of the signal of run-length 10. With setting of FF7 via the output of counter 6, low-speed clock ϕ1 is applied and the input picture signal is applied to register 13 for utilization of the output.
COPYRIGHT: (C)1979,JPO&Japio
JP2969278A 1978-03-13 1978-03-13 Decoder circuit Pending JPS54121020A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2969278A JPS54121020A (en) 1978-03-13 1978-03-13 Decoder circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2969278A JPS54121020A (en) 1978-03-13 1978-03-13 Decoder circuit

Publications (1)

Publication Number Publication Date
JPS54121020A true JPS54121020A (en) 1979-09-19

Family

ID=12283150

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2969278A Pending JPS54121020A (en) 1978-03-13 1978-03-13 Decoder circuit

Country Status (1)

Country Link
JP (1) JPS54121020A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961370A (en) * 1982-09-30 1984-04-07 Fujitsu Ltd Image data expanding system
JPS6181260U (en) * 1985-11-05 1986-05-29

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961370A (en) * 1982-09-30 1984-04-07 Fujitsu Ltd Image data expanding system
JPS6181260U (en) * 1985-11-05 1986-05-29
JPS6338604Y2 (en) * 1985-11-05 1988-10-12

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