JPS54103663A - Encoding circuit - Google Patents

Encoding circuit

Info

Publication number
JPS54103663A
JPS54103663A JP1127778A JP1127778A JPS54103663A JP S54103663 A JPS54103663 A JP S54103663A JP 1127778 A JP1127778 A JP 1127778A JP 1127778 A JP1127778 A JP 1127778A JP S54103663 A JPS54103663 A JP S54103663A
Authority
JP
Japan
Prior art keywords
signal
code
counter
memory
clock pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1127778A
Other languages
Japanese (ja)
Inventor
Hiroyuki Hayazaki
Noriyoshi Ogata
Masamichi Kawakami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP1127778A priority Critical patent/JPS54103663A/en
Publication of JPS54103663A publication Critical patent/JPS54103663A/en
Pending legal-status Critical Current

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  • Compression, Expansion, Code Conversion, And Decoders (AREA)

Abstract

PURPOSE: To compress the signal band width by transmitting the information signal such as the facsimile signal or the like after converted it into the code signal such as the modified Hoffman (MH) code or the like.
CONSTITUTION: Picture signal V of white-black binary type which is obtained from the manuscript and others is separated into white signal W and black signal B through separator circuit 1. The 1st counter 4 counts clock pulse 1 for measurement and is set and reset in accordance with the rise and fall of signal W. The MH code corresponding to each run length is stored in 1st memory 5, and the code which is obtained by reversing the binary code showing the bit number of each MH code is stored in 2nd memory 6 respectively. These two memories use the output of counter 4 as the address signal. The 2nd counter 8 counts clock pulse 2 for transmission and generates the carry output at the prescribed value to close gate 9. The MH code read out from memory 5 is loaded to shift register 7. This MH code is then read out by clock pulse 2 to be delivered through OR gate 10 in the form of the white signal.
COPYRIGHT: (C)1979,JPO&Japio
JP1127778A 1978-02-01 1978-02-01 Encoding circuit Pending JPS54103663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1127778A JPS54103663A (en) 1978-02-01 1978-02-01 Encoding circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1127778A JPS54103663A (en) 1978-02-01 1978-02-01 Encoding circuit

Publications (1)

Publication Number Publication Date
JPS54103663A true JPS54103663A (en) 1979-08-15

Family

ID=11773483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1127778A Pending JPS54103663A (en) 1978-02-01 1978-02-01 Encoding circuit

Country Status (1)

Country Link
JP (1) JPS54103663A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57174980A (en) * 1981-04-20 1982-10-27 Canon Inc Picture synthesizer
JPS58198968A (en) * 1982-05-14 1983-11-19 Canon Inc Image reproducing device
JPH0820296A (en) * 1995-05-08 1996-01-23 Youka Tekko Kk Motor-driven bicycle

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57174980A (en) * 1981-04-20 1982-10-27 Canon Inc Picture synthesizer
JPS58198968A (en) * 1982-05-14 1983-11-19 Canon Inc Image reproducing device
JPH0820296A (en) * 1995-05-08 1996-01-23 Youka Tekko Kk Motor-driven bicycle

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